From patchwork Mon Jun 19 14:46:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1796668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=YKkFSdRC; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QlCJv6nSRz20XZ for ; Tue, 20 Jun 2023 00:46:55 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E25A93858D38 for ; Mon, 19 Jun 2023 14:46:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E25A93858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687186013; bh=40it3mgVF18oeeexbaezrZ6v5SWOVxLYYRQReVmszxo=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=YKkFSdRClMzR4uT+f+MrFMsO+EFCnYKUMvwweGtlxiQ0wfNUac+E5kZkr5rgwvfd0 XdA94JM7zZCsWsGkBZesLob5GxvgtsPrRMh8geUpIeF+D5+M+fUwoZjm0cuAq0YIGC Zc+GWzex9RjmgpZ2mkazomlw7/hnrW263nXIpiNc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by sourceware.org (Postfix) with ESMTPS id CD5F038582BE for ; Mon, 19 Jun 2023 14:46:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CD5F038582BE Received: by mail-qk1-x733.google.com with SMTP id af79cd13be357-7623fdb3637so195687385a.2 for ; Mon, 19 Jun 2023 07:46:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687185990; x=1689777990; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=40it3mgVF18oeeexbaezrZ6v5SWOVxLYYRQReVmszxo=; b=lHF4XSrQweq209Q+jDGwtxsx2x6HP7gNjo5coh8rCIvLofcfdv/zBAQYPWyv5m8dWD FnYdQ7r80dsbFe2jfzEsUT90DVWWumYl+sfcI04Q7cKz6JNzWS70LFq6lH5ocqAMKrnm e2nNDhSakmFSlk2LHdmVvalNO4UkNqes8amVtUBhwRLusU5soFmvI3aSX6Y4Wn4QCpyA /Y+5lxDLuime+7TpN9dMh3GPwSmQN7sn/DlO+7/HuIKV3H/NY1/KJK3OnF1bB2CX1rVm E34BkuEBTJ7SQbD/jAwLLQDi/8NucXbczoHfK5im40ZFLgtXmhFAY/tpuWyATHoVys1b 2JGw== X-Gm-Message-State: AC+VfDwkBYmUrRp1AUcbmR0LoDuQvlUJYA3Hv1Wcd71H5Oni59HOKV6m AMeu1quff6xKYik/ZaPwgw8l2tX7PrheZZkc+AE45qi333BVbA== X-Google-Smtp-Source: ACHHUZ4vRDsr3IO5MC88csrfqLameQNFeSx7Y5MLZcfvY7ETjyusm1b3pcY9upJ9PXZ3shAMdKCs4IBXV8h/se6YQXM= X-Received: by 2002:ad4:5de8:0:b0:62d:f806:7f80 with SMTP id jn8-20020ad45de8000000b0062df8067f80mr10387104qvb.13.1687185989755; Mon, 19 Jun 2023 07:46:29 -0700 (PDT) MIME-Version: 1.0 Date: Mon, 19 Jun 2023 16:46:18 +0200 Message-ID: Subject: [committed] recog: Change return type of predicate functions from int to bool To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Also change some internal variables to bool and change return type of split_all_insns_noflow to void. gcc/ChangeLog: * recog.h (check_asm_operands): Change return type from int to bool. (insn_invalid_p): Ditto. (verify_changes): Ditto. (apply_change_group): Ditto. (constrain_operands): Ditto. (constrain_operands_cached): Ditto. (validate_replace_rtx_subexp): Ditto. (validate_replace_rtx): Ditto. (validate_replace_rtx_part): Ditto. (validate_replace_rtx_part_nosimplify): Ditto. (added_clobbers_hard_reg_p): Ditto. (peep2_regno_dead_p): Ditto. (peep2_reg_dead_p): Ditto. (store_data_bypass_p): Ditto. (if_test_bypass_p): Ditto. * rtl.h (split_all_insns_noflow): Change return type from unsigned int to void. * genemit.cc (output_added_clobbers_hard_reg_p): Change return type of generated added_clobbers_hard_reg_p from int to bool and adjust function body accordingly. Change "used" variable type from int to bool. * recog.cc (check_asm_operands): Change return type from int to bool and adjust function body accordingly. (insn_invalid_p): Ditto. Change "is_asm" variable to bool. (verify_changes): Change return type from int to bool. (apply_change_group): Change return type from int to bool and adjust function body accordingly. (validate_replace_rtx_subexp): Change return type from int to bool. (validate_replace_rtx): Ditto. (validate_replace_rtx_part): Ditto. (validate_replace_rtx_part_nosimplify): Ditto. (constrain_operands_cached): Ditto. (constrain_operands): Ditto. Change "lose" and "win" variables type from int to bool. (split_all_insns_noflow): Change return type from unsigned int to void and adjust function body accordingly. (peep2_regno_dead_p): Change return type from int to bool. (peep2_reg_dead_p): Ditto. (peep2_find_free_register): Change "success" variable type from int to bool (store_data_bypass_p_1): Change return type from int to bool. (store_data_bypass_p): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/genemit.cc b/gcc/genemit.cc index 33c9ec05d6f..1ce0564076d 100644 --- a/gcc/genemit.cc +++ b/gcc/genemit.cc @@ -688,26 +688,27 @@ output_added_clobbers_hard_reg_p (void) { struct clobber_pat *clobber; struct clobber_ent *ent; - int clobber_p, used; + int clobber_p; + bool used; - printf ("\n\nint\nadded_clobbers_hard_reg_p (int insn_code_number)\n"); + printf ("\n\nbool\nadded_clobbers_hard_reg_p (int insn_code_number)\n"); printf ("{\n"); printf (" switch (insn_code_number)\n"); printf (" {\n"); for (clobber_p = 0; clobber_p <= 1; clobber_p++) { - used = 0; + used = false; for (clobber = clobber_list; clobber; clobber = clobber->next) if (clobber->has_hard_reg == clobber_p) for (ent = clobber->insns; ent; ent = ent->next) { printf (" case %d:\n", ent->code_number); - used++; + used = true; } if (used) - printf (" return %d;\n\n", clobber_p); + printf (" return %s;\n\n", clobber_p ? "true" : "false"); } printf (" default:\n"); diff --git a/gcc/recog.cc b/gcc/recog.cc index fd09145d45e..37432087812 100644 --- a/gcc/recog.cc +++ b/gcc/recog.cc @@ -133,7 +133,7 @@ asm_labels_ok (rtx body) /* Check that X is an insn-body for an `asm' with operands and that the operands mentioned in it are legitimate. */ -int +bool check_asm_operands (rtx x) { int noperands; @@ -142,7 +142,7 @@ check_asm_operands (rtx x) int i; if (!asm_labels_ok (x)) - return 0; + return false; /* Post-reload, be more strict with things. */ if (reload_completed) @@ -156,9 +156,9 @@ check_asm_operands (rtx x) noperands = asm_noperands (x); if (noperands < 0) - return 0; + return false; if (noperands == 0) - return 1; + return true; operands = XALLOCAVEC (rtx, noperands); constraints = XALLOCAVEC (const char *, noperands); @@ -171,10 +171,10 @@ check_asm_operands (rtx x) if (c[0] == '%') c++; if (! asm_operand_ok (operands[i], c, constraints)) - return 0; + return false; } - return 1; + return true; } /* Static data for the next two routines. */ @@ -212,8 +212,8 @@ static int temporarily_undone_changes = 0; If IN_GROUP is zero, this is a single change. Try to recognize the insn or validate the memory reference with the change applied. If the result - is not valid for the machine, suppress the change and return zero. - Otherwise, perform the change and return 1. */ + is not valid for the machine, suppress the change and return false. + Otherwise, perform the change and return true. */ static bool validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, @@ -232,7 +232,7 @@ validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, if ((old == new_rtx || rtx_equal_p (old, new_rtx)) && (new_len < 0 || XVECLEN (new_rtx, 0) == new_len)) - return 1; + return true; gcc_assert ((in_group != 0 || num_changes == 0) && (new_len < 0 || new_rtx == *loc)); @@ -275,7 +275,7 @@ validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, change group we made. */ if (in_group) - return 1; + return true; else return apply_change_group (); } @@ -348,7 +348,7 @@ check_invalid_inc_dec (rtx reg, const_rtx, void *data) match the instructions will be added to the current change group. Otherwise the changes will take effect immediately. */ -int +bool insn_invalid_p (rtx_insn *insn, bool in_group) { rtx pat = PATTERN (insn); @@ -360,14 +360,14 @@ insn_invalid_p (rtx_insn *insn, bool in_group) && ! reload_completed && ! reload_in_progress) ? &num_clobbers : 0); - int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; + bool is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; /* If this is an asm and the operand aren't legal, then fail. Likewise if this is not an asm and the insn wasn't recognized. */ if ((is_asm && ! check_asm_operands (PATTERN (insn))) || (!is_asm && icode < 0)) - return 1; + return true; /* If we have to add CLOBBERs, fail if we have to add ones that reference hard registers since our callers can't know if they are live or not. @@ -377,7 +377,7 @@ insn_invalid_p (rtx_insn *insn, bool in_group) rtx newpat; if (added_clobbers_hard_reg_p (icode)) - return 1; + return true; newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1)); XVECEXP (newpat, 0, 0) = pat; @@ -394,7 +394,7 @@ insn_invalid_p (rtx_insn *insn, bool in_group) extract_insn (insn); if (! constrain_operands (1, get_preferred_alternatives (insn))) - return 1; + return true; } /* Punt if REG_INC argument overlaps some stored REG. */ @@ -405,11 +405,11 @@ insn_invalid_p (rtx_insn *insn, bool in_group) rtx reg = XEXP (link, 0); note_stores (insn, check_invalid_inc_dec, ®); if (reg == NULL_RTX) - return 1; + return true; } INSN_CODE (insn) = icode; - return 0; + return false; } /* Return number of changes made and not validated yet. */ @@ -420,9 +420,9 @@ num_changes_pending (void) } /* Tentatively apply the changes numbered NUM and up. - Return 1 if all changes are valid, zero otherwise. */ + Return true if all changes are valid, false otherwise. */ -int +bool verify_changes (int num) { int i; @@ -554,21 +554,21 @@ confirm_change_group (void) } /* Apply a group of changes previously issued with `validate_change'. - If all changes are valid, call confirm_change_group and return 1, - otherwise, call cancel_changes and return 0. */ + If all changes are valid, call confirm_change_group and return true, + otherwise, call cancel_changes and return false. */ -int +bool apply_change_group (void) { if (verify_changes (0)) { confirm_change_group (); - return 1; + return true; } else { cancel_changes (0); - return 0; + return false; } } @@ -894,7 +894,7 @@ validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object, with TO. After all changes have been made, validate by seeing if INSN is still valid. */ -int +bool validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc) { validate_replace_rtx_1 (loc, from, to, insn, true); @@ -904,7 +904,7 @@ validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc) /* Try replacing every occurrence of FROM in INSN with TO. After all changes have been made, validate by seeing if INSN is still valid. */ -int +bool validate_replace_rtx (rtx from, rtx to, rtx_insn *insn) { validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true); @@ -917,7 +917,7 @@ validate_replace_rtx (rtx from, rtx to, rtx_insn *insn) validate_replace_rtx (from, to, insn) is equivalent to validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */ -int +bool validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn) { validate_replace_rtx_1 (where, from, to, insn, true); @@ -925,7 +925,7 @@ validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn) } /* Same as above, but do not simplify rtx afterwards. */ -int +bool validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where, rtx_insn *insn) { @@ -953,7 +953,7 @@ struct validate_replace_src_data { rtx from; /* Old RTX */ rtx to; /* New RTX */ - rtx_insn *insn; /* Insn in which substitution is occurring. */ + rtx_insn *insn; /* Insn in which substitution is occurring. */ }; static void @@ -2705,13 +2705,13 @@ extract_constrain_insn_cached (rtx_insn *insn) } /* Do cached constrain_operands on INSN and complain about failures. */ -int +bool constrain_operands_cached (rtx_insn *insn, int strict) { if (which_alternative == -1) return constrain_operands (strict, get_enabled_alternatives (insn)); else - return 1; + return true; } /* Analyze INSN and fill in recog_data. */ @@ -3029,7 +3029,7 @@ struct funny_match int this_op, other; }; -int +bool constrain_operands (int strict, alternative_mask alternatives) { const char *constraints[MAX_RECOG_OPERANDS]; @@ -3042,7 +3042,7 @@ constrain_operands (int strict, alternative_mask alternatives) which_alternative = 0; if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) - return 1; + return true; for (c = 0; c < recog_data.n_operands; c++) constraints[c] = recog_data.constraints[c]; @@ -3051,7 +3051,7 @@ constrain_operands (int strict, alternative_mask alternatives) { int seen_earlyclobber_at = -1; int opno; - int lose = 0; + bool lose = false; funny_match_index = 0; if (!TEST_BIT (alternatives, which_alternative)) @@ -3074,7 +3074,7 @@ constrain_operands (int strict, alternative_mask alternatives) machine_mode mode = GET_MODE (op); const char *p = constraints[opno]; int offset = 0; - int win = 0; + bool win = false; int val; int len; @@ -3101,7 +3101,7 @@ constrain_operands (int strict, alternative_mask alternatives) /* An empty constraint or empty alternative allows anything which matched the pattern. */ if (*p == 0 || *p == ',') - win = 1; + win = true; do switch (c = *p, len = CONSTRAINT_LEN (c, p), c) @@ -3167,7 +3167,7 @@ constrain_operands (int strict, alternative_mask alternatives) matching_operands[match] = opno; if (val != 0) - win = 1; + win = true; /* If output is *x and input is *--x, arrange later to change the output to *--x as well, since the @@ -3192,7 +3192,7 @@ constrain_operands (int strict, alternative_mask alternatives) && (strict <= 0 || (strict_memory_address_p (recog_data.operand_mode[opno], op)))) - win = 1; + win = true; break; /* No need to check general_operand again; @@ -3209,10 +3209,10 @@ constrain_operands (int strict, alternative_mask alternatives) || (reload_in_progress && REGNO (op) >= FIRST_PSEUDO_REGISTER) || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) - win = 1; + win = true; } else if (strict < 0 || general_operand (op, mode)) - win = 1; + win = true; break; default: @@ -3228,11 +3228,11 @@ constrain_operands (int strict, alternative_mask alternatives) || (strict == 0 && GET_CODE (op) == SCRATCH) || (REG_P (op) && reg_fits_class_p (op, cl, offset, mode))) - win = 1; + win = true; } else if (constraint_satisfied_p (op, cn)) - win = 1; + win = true; else if ((insn_extra_memory_constraint (cn) || insn_extra_relaxed_memory_constraint (cn)) @@ -3247,11 +3247,11 @@ constrain_operands (int strict, alternative_mask alternatives) /* During reload, accept a pseudo */ || (reload_in_progress && REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))) - win = 1; + win = true; else if (insn_extra_address_constraint (cn) /* Every address operand can be reloaded to fit. */ && strict < 0) - win = 1; + win = true; /* Cater to architectures like IA-64 that define extra memory constraints without using define_memory_constraint. */ else if (reload_in_progress @@ -3261,7 +3261,7 @@ constrain_operands (int strict, alternative_mask alternatives) && reg_equiv_mem (REGNO (op)) != 0 && constraint_satisfied_p (reg_equiv_mem (REGNO (op)), cn)) - win = 1; + win = true; break; } } @@ -3271,7 +3271,7 @@ constrain_operands (int strict, alternative_mask alternatives) /* If this operand did not win somehow, this alternative loses. */ if (! win) - lose = 1; + lose = true; } /* This alternative won; the operands are ok. Change whichever operands this alternative says to change. */ @@ -3302,7 +3302,7 @@ constrain_operands (int strict, alternative_mask alternatives) recog_data.operand[eopno])) && ! safe_from_earlyclobber (recog_data.operand[opno], recog_data.operand[eopno])) - lose = 1; + lose = true; if (! lose) { @@ -3328,14 +3328,14 @@ constrain_operands (int strict, alternative_mask alternatives) if (strchr (recog_data.constraints[opno], '<') == NULL && strchr (recog_data.constraints[opno], '>') == NULL) - return 0; + return false; break; default: break; } } - return 1; + return true; } } @@ -3349,7 +3349,7 @@ constrain_operands (int strict, alternative_mask alternatives) if (strict == 0) return constrain_operands (-1, alternatives); else - return 0; + return false; } /* Return true iff OPERAND (assumed to be a REG rtx) @@ -3517,7 +3517,7 @@ split_all_insns (void) /* Same as split_all_insns, but do not expect CFG to be available. Used by machine dependent reorg passes. */ -unsigned int +void split_all_insns_noflow (void) { rtx_insn *next, *insn; @@ -3547,7 +3547,6 @@ split_all_insns_noflow (void) split_insn (insn); } } - return 0; } struct peep2_insn_data @@ -3596,7 +3595,7 @@ peep2_next_insn (int n) /* Return true if REGNO is dead before the Nth non-note insn after `current'. */ -int +bool peep2_regno_dead_p (int ofs, int regno) { gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); @@ -3610,7 +3609,7 @@ peep2_regno_dead_p (int ofs, int regno) /* Similarly for a REG. */ -int +bool peep2_reg_dead_p (int ofs, rtx reg) { gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); @@ -3622,8 +3621,8 @@ peep2_reg_dead_p (int ofs, rtx reg) unsigned int end_regno = END_REGNO (reg); for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno)) - return 0; - return 1; + return false; + return true; } /* Regno offset to be used in the register search. */ @@ -3673,7 +3672,8 @@ peep2_find_free_register (int from, int to, const char *class_str, for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) { - int raw_regno, regno, success, j; + int raw_regno, regno, j; + bool success; /* Distribute the free registers as much as possible. */ raw_regno = search_ofs + i; @@ -3689,38 +3689,38 @@ peep2_find_free_register (int from, int to, const char *class_str, if (!targetm.hard_regno_mode_ok (regno, mode)) continue; - success = 1; + success = true; for (j = 0; success && j < hard_regno_nregs (regno, mode); j++) { /* Don't allocate fixed registers. */ if (fixed_regs[regno + j]) { - success = 0; + success = false; break; } /* Don't allocate global registers. */ if (global_regs[regno + j]) { - success = 0; + success = false; break; } /* Make sure the register is of the right class. */ if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j)) { - success = 0; + success = false; break; } /* And that we don't create an extra save/restore. */ if (! crtl->abi->clobbers_full_reg_p (regno + j) && ! df_regs_ever_live_p (regno + j)) { - success = 0; + success = false; break; } if (! targetm.hard_regno_scratch_ok (regno + j)) { - success = 0; + success = false; break; } @@ -3729,14 +3729,14 @@ peep2_find_free_register (int from, int to, const char *class_str, || regno + j == HARD_FRAME_POINTER_REGNUM) && (! reload_completed || frame_pointer_needed)) { - success = 0; + success = false; break; } if (TEST_HARD_REG_BIT (*reg_set, regno + j) || TEST_HARD_REG_BIT (live, regno + j)) { - success = 0; + success = false; break; } } @@ -4244,7 +4244,7 @@ store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set) data not the address operand(s) of the store. IN_INSN and OUT_INSN must be either a single_set or a PARALLEL with SETs inside. */ -int +bool store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) { rtx in_set = single_set (in_insn); @@ -4276,7 +4276,7 @@ store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) or multiple set; IN_INSN should be single_set for truth, but for convenience of insn categorization may be any JUMP or CALL insn. */ -int +bool if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) { rtx out_set, in_set; @@ -4618,7 +4618,8 @@ public: unsigned int execute (function *) final override { - return split_all_insns_noflow (); + split_all_insns_noflow (); + return 0; } }; // class pass_split_for_shorten_branches diff --git a/gcc/recog.h b/gcc/recog.h index 539a27c3edf..badf8e3dc1c 100644 --- a/gcc/recog.h +++ b/gcc/recog.h @@ -184,22 +184,22 @@ inline insn_propagation::insn_propagation (rtx_insn *insn) extern void init_recog (void); extern void init_recog_no_volatile (void); -extern int check_asm_operands (rtx); +extern bool check_asm_operands (rtx); extern int asm_operand_ok (rtx, const char *, const char **); extern bool validate_change (rtx, rtx *, rtx, bool); extern bool validate_unshare_change (rtx, rtx *, rtx, bool); extern bool validate_change_xveclen (rtx, rtx *, int, bool); extern bool canonicalize_change_group (rtx_insn *insn, rtx x); -extern int insn_invalid_p (rtx_insn *, bool); -extern int verify_changes (int); +extern bool insn_invalid_p (rtx_insn *, bool); +extern bool verify_changes (int); extern void confirm_change_group (void); -extern int apply_change_group (void); +extern bool apply_change_group (void); extern int num_validated_changes (void); extern void cancel_changes (int); extern void temporarily_undo_changes (int); extern void redo_changes (int); -extern int constrain_operands (int, alternative_mask); -extern int constrain_operands_cached (rtx_insn *, int); +extern bool constrain_operands (int, alternative_mask); +extern bool constrain_operands_cached (rtx_insn *, int); extern bool memory_address_addr_space_p (machine_mode, rtx, addr_space_t); #define memory_address_p(mode,addr) \ memory_address_addr_space_p ((mode), (addr), ADDR_SPACE_GENERIC) @@ -207,10 +207,10 @@ extern bool strict_memory_address_addr_space_p (machine_mode, rtx, addr_space_t); #define strict_memory_address_p(mode,addr) \ strict_memory_address_addr_space_p ((mode), (addr), ADDR_SPACE_GENERIC) -extern int validate_replace_rtx_subexp (rtx, rtx, rtx_insn *, rtx *); -extern int validate_replace_rtx (rtx, rtx, rtx_insn *); -extern int validate_replace_rtx_part (rtx, rtx, rtx *, rtx_insn *); -extern int validate_replace_rtx_part_nosimplify (rtx, rtx, rtx *, rtx_insn *); +extern bool validate_replace_rtx_subexp (rtx, rtx, rtx_insn *, rtx *); +extern bool validate_replace_rtx (rtx, rtx, rtx_insn *); +extern bool validate_replace_rtx_part (rtx, rtx, rtx *, rtx_insn *); +extern bool validate_replace_rtx_part_nosimplify (rtx, rtx, rtx *, rtx_insn *); extern void validate_replace_rtx_group (rtx, rtx, rtx_insn *); extern void validate_replace_src_group (rtx, rtx, rtx_insn *); extern bool validate_simplify_insn (rtx_insn *insn); @@ -232,7 +232,7 @@ extern int recog (rtx, rtx_insn *, int *); inline int recog_memoized (rtx_insn *insn); #endif extern void add_clobbers (rtx, int); -extern int added_clobbers_hard_reg_p (int); +extern bool added_clobbers_hard_reg_p (int); extern void insn_extract (rtx_insn *); extern void extract_insn (rtx_insn *); extern void extract_constrain_insn (rtx_insn *insn); @@ -243,16 +243,16 @@ extern void preprocess_constraints (int, int, const char **, extern const operand_alternative *preprocess_insn_constraints (unsigned int); extern void preprocess_constraints (rtx_insn *); extern rtx_insn *peep2_next_insn (int); -extern int peep2_regno_dead_p (int, int); -extern int peep2_reg_dead_p (int, rtx); +extern bool peep2_regno_dead_p (int, int); +extern bool peep2_reg_dead_p (int, rtx); #ifdef HARD_CONST extern rtx peep2_find_free_register (int, int, const char *, machine_mode, HARD_REG_SET *); #endif extern rtx_insn *peephole2_insns (rtx, rtx_insn *, int *); -extern int store_data_bypass_p (rtx_insn *, rtx_insn *); -extern int if_test_bypass_p (rtx_insn *, rtx_insn *); +extern bool store_data_bypass_p (rtx_insn *, rtx_insn *); +extern bool if_test_bypass_p (rtx_insn *, rtx_insn *); extern void copy_frame_info_to_split_insn (rtx_insn *, rtx_insn *); diff --git a/gcc/rtl.h b/gcc/rtl.h index f66744b18e3..9c6803f043e 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -3795,7 +3795,7 @@ extern void setup_reg_classes (int, enum reg_class, enum reg_class, enum reg_class); extern void split_all_insns (void); -extern unsigned int split_all_insns_noflow (void); +extern void split_all_insns_noflow (void); #define MAX_SAVED_CONST_INT 64 extern GTY(()) rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];