===================================================================
@@ -11471,6 +11471,40 @@
(match_dup 3))
(set (reg:SI SP_REG) (match_dup 4))])])
+;; Combining simple memory jump instruction
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (set (pc) (match_dup 0))]
+ "!TARGET_64BIT && peep2_reg_dead_p (2, operands[0])"
+ [(set (pc) (match_dup 1))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (pc) (match_dup 0))]
+ "!TARGET_64BIT && peep2_reg_dead_p (3, operands[0])"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (pc) (match_dup 1))])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_nox32_operand"))
+ (set (pc) (match_dup 0))]
+ "TARGET_64BIT && peep2_reg_dead_p (2, operands[0])"
+ [(set (pc) (match_dup 1))])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (pc) (match_dup 0))]
+ "TARGET_64BIT && peep2_reg_dead_p (3, operands[0])"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (pc) (match_dup 1))])
+
;; Call subroutine, returning value in operand 0
(define_expand "call_value"
===================================================================
@@ -0,0 +1,23 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2" } */
+
+#define ADVANCE_AND_DISPATCH() goto *addresses[*pc++]
+
+void
+Interpret(const unsigned char *pc)
+{
+ static const void *const addresses[] = {
+ &&l0, &&l1, &&l2
+ };
+
+l0:
+ ADVANCE_AND_DISPATCH();
+
+l1:
+ ADVANCE_AND_DISPATCH();
+
+l2:
+ return;
+}
+
+/* { dg-final { scan-assembler-not "jmp\[ \t\]*.%eax" } } */