diff mbox series

[avr] Fix PR84209 code issue due to post-reload split of SP into 2 QI regs

Message ID CADOs=zZLMfLzdt8yykoYjhx3utseEv9viSod-VMDoXc4KezunQ@mail.gmail.com
State New
Headers show
Series [avr] Fix PR84209 code issue due to post-reload split of SP into 2 QI regs | expand

Commit Message

Denis Chertykov Feb. 7, 2018, 10:03 a.m. UTC 
Committed.

2018-01-09  Georg-Johann Lay  <avr@gjlay.de>

PR target/84209
        * config/avr/avr.h (GENERAL_REGNO_P, GENERAL_REG_P): New macros.
        * config/avr/avr.md: Only post-reload split REG-REG moves if
        either register is REGERAL_REG_P.
diff mbox series

Patch

--- config/avr/avr.h (revision 257384)
+++ config/avr/avr.h (working copy)
@@ -153,6 +153,9 @@  These two properties are reflected by bu

 #define FIRST_PSEUDO_REGISTER 36

+#define GENERAL_REGNO_P(N) IN_RANGE (N, 2, 31)
+#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
+
 #define FIXED_REGISTERS {\
   1,1,/* r0 r1 */\
   0,0,/* r2 r3 */\
--- config/avr/avr.md (revision 257384)
+++ config/avr/avr.md (working copy)
@@ -3362,6 +3362,8 @@  (define_split
         (match_operand:HI 1 "reg_or_0_operand"))]
   "optimize
    && reload_completed
+   && GENERAL_REG_P (operands[0])
+   && (operands[1] == const0_rtx || GENERAL_REG_P (operands[1]))
    && (!AVR_HAVE_MOVW
        || const0_rtx == operands[1])"
   [(set (match_dup 2) (match_dup 3))