From patchwork Tue Mar 18 08:16:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenqiang Chen X-Patchwork-Id: 331341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 284AB2C007C for ; Tue, 18 Mar 2014 19:16:16 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; q=dns; s=default; b=d8zEJMuVjVyc9X6q+Z+hgYWYtO5hJ9oFOhaPwsCT9XG ssqkAYtymRRzSuX++Z2TPZbA+jXTdt9dsForhLoUEGar8rVAFQLRar6T1jroDjBj W57/gqyF0ZN/k38uLXpvXaeiWC/MUOVdnC4U7XeewYC3jyWYQeyis8FfnsZkga1A = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; s=default; bh=OmYLC611v7wYcK9eCPOWRqNqxZA=; b=fi2xsZfA+0nsnIlTa sRVynfkZn2s0By2MymjnokVEfbVz5rKBPVgEcUyETqlsFxTjiXEPL8YLsViammVD QiU4T6kpDQoP/DSbnDLKwhJdX/1MRHNw5mipD5jzxWhLANVZe0u5Qp1qAzdIErb7 MofrYcrnkC8MfmCUrqOjnJixhE= Received: (qmail 25059 invoked by alias); 18 Mar 2014 08:16:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25048 invoked by uid 89); 18 Mar 2014 08:16:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-la0-f50.google.com Received: from mail-la0-f50.google.com (HELO mail-la0-f50.google.com) (209.85.215.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 18 Mar 2014 08:16:07 +0000 Received: by mail-la0-f50.google.com with SMTP id y1so4479948lam.37 for ; Tue, 18 Mar 2014 01:16:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to:cc :content-type; bh=/WiL1IQHO4t6uJEn/pP0k/MltLYOuRIgRa2oamTdnDw=; b=QW5+GT82GVkQTh0lPx2WXvXGwa0CzIqtqIaYNt2XKgrdSjm30hCq4zrMStQzdtB/Z0 DBrQcBnxi6L09gIyd314KIUBbPgr3kkATo/AqBckn552+4V87Wul27Qe/mfabJ51/sB7 NRqF2XsU7YuYIZV9+Rcr1gekSTkUuFDpYI6edVr5DVao9peRT1qvLpp1PfNYjtsQ+G1S 5qfYM6QoXERlMzLoiUasrGxS+wpZG8TokdykgZJmX1kzBW5UIZl6Oy6NjZds/miLNhEL BgPfINoSH5mujUtZjlcudrio4UmAsqy9d9i2DWQTTLmrxTD65APLG7wIWhBrMCLIyMPG wuhQ== X-Gm-Message-State: ALoCoQkgjAKQ/J2Rr59wFHElwtlqYR304BX40P9cCxq+GRKsOfZmd91w0b/8m4sCb8j6I1xKkwIL MIME-Version: 1.0 X-Received: by 10.152.87.14 with SMTP id t14mr51011laz.52.1395130563548; Tue, 18 Mar 2014 01:16:03 -0700 (PDT) Received: by 10.112.135.105 with HTTP; Tue, 18 Mar 2014 01:16:03 -0700 (PDT) Date: Tue, 18 Mar 2014 16:16:03 +0800 Message-ID: Subject: [PATCH, AARCH64] movcc for fcsel From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" Cc: Marcus Shawcroft , Richard Earnshaw X-IsSubscribed: yes Hi, For float value, movsfcc/movdfcc is required by emit_conditional_move called in ifcvt pass to expand if-then-else to "fcsel" insn. Bootstrap and no make check regression with qemu-aarch64. Is it OK for next stage1? Thanks! -Zhenqiang ChangeLog: 2014-03-18 Zhenqiang Chen * config/aarch64/aarch64.md (movcc): New for GPF. testsuite/ChangeLog: 2014-03-18 Zhenqiang Chen * gcc.target/aarch64/fcsel.c: New test case. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 99a6ac8..0f4b8ebf 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2344,6 +2344,25 @@ } ) +(define_expand "movcc" + [(set (match_operand:GPF 0 "register_operand" "") + (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "") + (match_operand:GPF 2 "register_operand" "") + (match_operand:GPF 3 "register_operand" "")))] + "" + { + rtx ccreg; + enum rtx_code code = GET_CODE (operands[1]); + + if (code == UNEQ || code == LTGT) + FAIL; + + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + } +) + (define_insn "*csinc2_insn" [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator" diff --git a/gcc/testsuite/gcc.target/aarch64/fcsel.c b/gcc/testsuite/gcc.target/aarch64/fcsel.c new file mode 100644 index 0000000..9c5431a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fcsel.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +float f1 (float a, float b, float c, float d) +{ + if (a > 0.0) + return c; + else + return 2.0; +} + +double f2 (double a, double b, double c, double d) +{ + if (a > b) + return c; + else + return d; +} + +/* { dg-final { scan-assembler-times "\tfcsel" 2 } } */