From patchwork Tue Aug 5 09:31:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenqiang Chen X-Patchwork-Id: 376634 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3070814008B for ; Tue, 5 Aug 2014 19:31:42 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=RaZloo573RDggb93ISeehHiIkIXSmuVf/svvkAFeaVI8Cx K6I06rKAc7Ka6z8lAxafj16xejG0HJaEapy0jhpzDtKqS8LjCYOti9CtfFCap9Y4 S1wB3TYIrWYFsNO+zV8uFhi5mBcpgARvvRlpCgQT8cqMqwBemIk/nQu9nFFaI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=q64RixU8uq8ZTpV7G65Hb6vAvXQ=; b=B1Rua5rnygSrE3kiQ2pN 79b6pEtIl1QXE9QrwieLkm/xa3YfecTBmsYwgJgnJp5TlyqTrUCQej7h98NQjiR7 vZRpo5AKr70ytpLCW70Ige9lgjYL36bW6Goq+9cssv6wxRgADqVZ2duR11HgX+mA 7j0Z3ZS37/jbh10KfWaqCKo= Received: (qmail 14007 invoked by alias); 5 Aug 2014 09:31:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13991 invoked by uid 89); 5 Aug 2014 09:31:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f179.google.com Received: from mail-lb0-f179.google.com (HELO mail-lb0-f179.google.com) (209.85.217.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 05 Aug 2014 09:31:27 +0000 Received: by mail-lb0-f179.google.com with SMTP id v6so496462lbi.10 for ; Tue, 05 Aug 2014 02:31:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to :content-type; bh=R9bVzzdjvepID8D8NPyK3WwlSKQe+ctMqLoMM2afblM=; b=YMdhSuyd8XOOIyuT4YejsRgwIkQb8KD/fujMU5/+Jq44I5P/Pdane6kBV9qMJ7dhth tjLpgVr23k2BG0tj9R9DMHgxtTOgQw2tjDZieY5m/VY65Aq7jVzpuU6Dg8taSed0cOsK EKnV6XaswOOjA6kIR6lGXd1q+JwrUCh/JstOr6un+XSgNgi7jp5nbBlWrtViV1/SJ3qh +tCe/wekFaFTYEq0FZRq9G4DSTiVz2uC4NYNG1Mi+kzP+smlkcxTsB+7AENupvuLxnXW JdAr6kY/TBtpwbN+cG8O4k/WRYCDi4Z4JTnmcdQn9JlfaBREUN2A3XOoNHm/CZYNrQ9J GCAw== X-Gm-Message-State: ALoCoQmFvgsRhgYVCAvnmOd7sp9WUJSrbUwGwFfR6zkk+VWk/33bIAh1w6l62SDo+SXX+3Wr8FUJ MIME-Version: 1.0 X-Received: by 10.152.4.97 with SMTP id j1mr2823905laj.10.1407231082873; Tue, 05 Aug 2014 02:31:22 -0700 (PDT) Received: by 10.112.136.66 with HTTP; Tue, 5 Aug 2014 02:31:22 -0700 (PDT) Date: Tue, 5 Aug 2014 17:31:22 +0800 Message-ID: Subject: [PATCH, ARM] Keep constants in register when expanding From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes Hi, For some large constants, ARM will split them during expanding, which makes impossible to hoist them out the loop or shared by different references (refer the test case in the patch). The patch keeps some constants in registers. If the constant can not be optimized, the cprop and combine passes can optimize them as what we do in current expand pass with define_insn_and_split "*arm_subsi3_insn" define_insn_and_split "*arm_andsi3_insn" define_insn_and_split "*iorsi3_insn" define_insn_and_split "*arm_xorsi3" The patch does not modify addsi3 since the define_insn_and_split "*arm_addsi3" is only valid when (reload_completed || !arm_eliminable_register (operands[1])). The cprop and combine passes can not optimize the large constant if we put it in register, which will lead to regression. For logic operators, the patch skips changes for constants: INTVAL (operands[2]) < 0 && const_ok_for_arm (-INTVAL (operands[2]) since expand pass always uses "sign-extend" to get the value (trunc_int_for_mode called from immed_wide_int_const) for rtl, and logs show most negative values are UNSIGNED when they are TREE node. And combine pass is smart enough to recover the negative value to positive value. Bootstrap and no make check regression on Chrome book. For coremark, dhrystone and eembcv1, no any code size and performance change on Cortex-M4. No any file in CSiBE has code size change for Cortex-A15 and Cortex-M4. No Spec2000 performance regression on Chrome book and dumped assemble codes only show very few difference. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-08-05 Zhenqiang Chen * config/arm/arm.md (subsi3, andsi3, iorsi3, xorsi3): Keep some large constants in register other than split them. testsuite/ChangeLog: 2014-08-05 Zhenqiang Chen * gcc.target/arm/maskdata.c: New test. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index bd8ea8f..c8b3001 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1162,9 +1162,16 @@ { if (TARGET_32BIT) { - arm_split_constant (MINUS, SImode, NULL_RTX, - INTVAL (operands[1]), operands[0], - operands[2], optimize && can_create_pseudo_p ()); + if (!const_ok_for_arm (INTVAL (operands[1])) + && can_create_pseudo_p ()) + { + operands[1] = force_reg (SImode, operands[1]); + emit_insn (gen_subsi3 (operands[0], operands[1], operands[2])); + } + else + arm_split_constant (MINUS, SImode, NULL_RTX, + INTVAL (operands[1]), operands[0], operands[2], + optimize && can_create_pseudo_p ()); DONE; } else /* TARGET_THUMB1 */ @@ -2077,6 +2084,17 @@ emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0], operands[1])); } + else if (!(const_ok_for_arm (INTVAL (operands[2])) + || const_ok_for_arm (~INTVAL (operands[2])) + /* zero_extendhi instruction is efficient enough. */ + || INTVAL (operands[2]) == 0xffff + || (INTVAL (operands[2]) < 0 + && const_ok_for_arm (-INTVAL (operands[2])))) + && can_create_pseudo_p ()) + { + operands[2] = force_reg (SImode, operands[2]); + emit_insn (gen_andsi3 (operands[0], operands[1], operands[2])); + } else arm_split_constant (AND, SImode, NULL_RTX, INTVAL (operands[2]), operands[0], @@ -2882,9 +2900,20 @@ { if (TARGET_32BIT) { - arm_split_constant (IOR, SImode, NULL_RTX, - INTVAL (operands[2]), operands[0], operands[1], - optimize && can_create_pseudo_p ()); + if (!(const_ok_for_arm (INTVAL (operands[2])) + || (TARGET_THUMB2 + && const_ok_for_arm (~INTVAL (operands[2]))) + || (INTVAL (operands[2]) < 0 + && const_ok_for_arm (-INTVAL (operands[2])))) + && can_create_pseudo_p ()) + { + operands[2] = force_reg (SImode, operands[2]); + emit_insn (gen_iorsi3 (operands[0], operands[1], operands[2])); + } + else + arm_split_constant (IOR, SImode, NULL_RTX, + INTVAL (operands[2]), operands[0], operands[1], + optimize && can_create_pseudo_p ()); DONE; } else /* TARGET_THUMB1 */ @@ -3052,9 +3081,18 @@ { if (TARGET_32BIT) { - arm_split_constant (XOR, SImode, NULL_RTX, - INTVAL (operands[2]), operands[0], operands[1], - optimize && can_create_pseudo_p ()); + if (!(const_ok_for_arm (INTVAL (operands[2])) + || (INTVAL (operands[2]) < 0 + && const_ok_for_arm (-INTVAL (operands[2])))) + && can_create_pseudo_p ()) + { + operands[2] = force_reg (SImode, operands[2]); + emit_insn (gen_xorsi3 (operands[0], operands[1], operands[2])); + } + else + arm_split_constant (XOR, SImode, NULL_RTX, + INTVAL (operands[2]), operands[0], operands[1], + optimize && can_create_pseudo_p ()); DONE; } else /* TARGET_THUMB1 */ diff --git a/gcc/testsuite/gcc.target/arm/maskdata.c b/gcc/testsuite/gcc.target/arm/maskdata.c new file mode 100644 index 0000000..b4231a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/maskdata.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 -fno-gcse " } */ +/* { dg-require-effective-target arm_thumb2_ok } */ + +#define MASK 0xfe00ff +void maskdata (int * data, int len) +{ + int i = len; + for (; i > 0; i -= 2) + { + data[i] &= MASK; + data[i + 1] &= MASK; + } +} +/* { dg-final { scan-assembler "254" } } */ +/* { dg-final { scan-assembler "255" } } */