From patchwork Mon Jun 23 07:00:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenqiang Chen X-Patchwork-Id: 362670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 59CB014009B for ; Mon, 23 Jun 2014 17:00:49 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=FgfSOv7VuqDXbdMUKfbLxYIqXXPkFDMrcr4hUNMt73ms2z XACsvtYUUL/Ah20urIFivzDbCP39VwxJJPPg9mHWl/VQSHb7mA16aPt+d2fv/co2 wTyM41bny6FLwVn9bnGYX2leC8rB9Amm7maMmT7ftLXLQYCoPkrMuhnOOhgt0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=ugpYhRP6xkUa1bvRdOwS0n/n8uE=; b=S4jqDpGr5EPMT3GFQUqX 9+h/Gd6TFIGXkZ5TAaWbrXVpWIrEJBC0v5mfc2aMvOo4dF2NMw7V0S++6kF7NLyR dMou2EaHKgHRbz6M+zFsGVwAFoBt8Igk4qxKQ72Rkq8xo6IPn2VtVtphNuOOvGhZ lXBaIA2AdhAHS9YNvf3+PEM= Received: (qmail 15215 invoked by alias); 23 Jun 2014 07:00:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15202 invoked by uid 89); 23 Jun 2014 07:00:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f181.google.com Received: from mail-lb0-f181.google.com (HELO mail-lb0-f181.google.com) (209.85.217.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 23 Jun 2014 07:00:13 +0000 Received: by mail-lb0-f181.google.com with SMTP id p9so3809218lbv.26 for ; Mon, 23 Jun 2014 00:00:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to :content-type; bh=muEMlWklHpkiihBdF8zLpfhZ2eqo5NNcBtKTpWRL5Yo=; b=iS8T0oo7k1vI9UFaJZQXJHqf+9EJzd9pT+xibgIRbvkEPpbAKMHgw5XD6k2jeMn7mu a3gdU8L5oKTlIqqyZ9TsTp2V0lOD0SPmQzvrQfLehWeiR3n5+gk22H1bB4SB0TMXYAIw MFHfp7b6xmt7+95USvD+1oAfKY37F8cPI5Y4ttqNS70Mr20JC3lObGyyzaDcWGA3VEPR Dplq0jdOVdqP5mgap7P9tSSV/atzdNQU1oPFbXGfAKiL+2QUNWcvVXF4Sr0FwK/yz/QH 2Kse/ch6BgEhhd28R7xdzwCaUQLL2fHXRUyGBgGiQwdqoQe7ZKNFrEwvVmYknwmzNNFA 0v4w== X-Gm-Message-State: ALoCoQmTMQS5pdYN0UINSD6Wtm5WG7lfrtHtpAcdEq2K8mAhJE3tuHdqfS0UUUhG+vsFWti/JE4B MIME-Version: 1.0 X-Received: by 10.112.162.70 with SMTP id xy6mr15159749lbb.40.1403506809874; Mon, 23 Jun 2014 00:00:09 -0700 (PDT) Received: by 10.112.13.36 with HTTP; Mon, 23 Jun 2014 00:00:09 -0700 (PDT) Date: Mon, 23 Jun 2014 15:00:09 +0800 Message-ID: Subject: [PATCH, 6/10] aarch64: add ccmp CC mode From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes Hi, The patches add a set of CC mode for AARCH64, which is similar as them for ARM. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-06-23 Zhenqiang Chen * config/aarch64/aarch64-modes.def: Define new CC modes for ccmp. * config/aarch64/aarch64.c (aarch64_get_condition_code_1): New prototype. (aarch64_get_condition_code): Call aarch64_get_condition_code_1. (aarch64_get_condition_code_1): New function to handle ccmp CC mode. * config/aarch64/predicates.md (ccmp_cc_register): New. diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index 1d2cc76..71fd2f0 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -25,6 +25,16 @@ CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */ CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */ CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */ +CC_MODE (CC_DNE); +CC_MODE (CC_DEQ); +CC_MODE (CC_DLE); +CC_MODE (CC_DLT); +CC_MODE (CC_DGE); +CC_MODE (CC_DGT); +CC_MODE (CC_DLEU); +CC_MODE (CC_DLTU); +CC_MODE (CC_DGEU); +CC_MODE (CC_DGTU); /* Vector modes. */ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ecf88f9..e5ede6e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3460,6 +3460,9 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) } static unsigned +aarch64_get_condition_code_1 (enum machine_mode, enum rtx_code); + +static unsigned aarch64_get_condition_code (rtx x) { enum machine_mode mode = GET_MODE (XEXP (x, 0)); @@ -3467,7 +3470,12 @@ aarch64_get_condition_code (rtx x) if (GET_MODE_CLASS (mode) != MODE_CC) mode = SELECT_CC_MODE (comp_code, XEXP (x, 0), XEXP (x, 1)); + return aarch64_get_condition_code_1 (mode, comp_code); +} +static unsigned +aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code) +{ switch (mode) { case CCFPmode: @@ -3490,6 +3498,27 @@ aarch64_get_condition_code (rtx x) } break; + case CC_DNEmode: + return comp_code == NE ? AARCH64_NE : AARCH64_EQ; + case CC_DEQmode: + return comp_code == NE ? AARCH64_EQ : AARCH64_NE; + case CC_DGEmode: + return comp_code == NE ? AARCH64_GE : AARCH64_LT; + case CC_DLTmode: + return comp_code == NE ? AARCH64_LT : AARCH64_GE; + case CC_DGTmode: + return comp_code == NE ? AARCH64_GT : AARCH64_LE; + case CC_DLEmode: + return comp_code == NE ? AARCH64_LE : AARCH64_GT; + case CC_DGEUmode: + return comp_code == NE ? AARCH64_CS : AARCH64_CC; + case CC_DLTUmode: + return comp_code == NE ? AARCH64_CC : AARCH64_CS; + case CC_DGTUmode: + return comp_code == NE ? AARCH64_HI : AARCH64_LS; + case CC_DLEUmode: + return comp_code == NE ? AARCH64_LS : AARCH64_HI; + case CCmode: switch (comp_code) { diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index dd35714..ab02fd0 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -39,6 +39,23 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_ccmp_immediate"))) +(define_special_predicate "ccmp_cc_register" + (and (match_code "reg") + (and (match_test "REGNO (op) == CC_REGNUM") + (ior (match_test "mode == GET_MODE (op)") + (match_test "mode == VOIDmode + && (GET_MODE (op) == CC_DNEmode + || GET_MODE (op) == CC_DEQmode + || GET_MODE (op) == CC_DLEmode + || GET_MODE (op) == CC_DLTmode + || GET_MODE (op) == CC_DGEmode + || GET_MODE (op) == CC_DGTmode + || GET_MODE (op) == CC_DLEUmode + || GET_MODE (op) == CC_DLTUmode + || GET_MODE (op) == CC_DGEUmode + || GET_MODE (op) == CC_DGTUmode)")))) +) + (define_predicate "aarch64_simd_register" (and (match_code "reg") (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")