From patchwork Fri Jun 23 21:46:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 780288 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wvX8N2Wbrz9s7h for ; Sat, 24 Jun 2017 07:46:28 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="j+XI3SR3"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=HbSPO8D+uQgJorN VpjLnmOPxXpouSOCOM6VkuOftZNFegFa6vHmJwsYmSOYzdrwXWf5QLti13unomNf +HUaeg4hlW8ENDbYiNCAt+BPm8hX3LK1Z7wT+GbABXAtLhfARIxl1192p0kCM2jj cFYuYoo4ARAz3k7GwFXPlub/T+RE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; s=default; bh=J6YCiDnkQVJPwIziy86lN 5BFrJY=; b=j+XI3SR31Dx2rwSOIWKe3dXrw9LRqqhOBFi2QsvswENWoGmm/fs27 TUORO7viPxNrQtB8Zyyf9Avif01XFABOyvoRS/ft5YOVu6C0peJ+qyRM+YKZ0hB7 zOxhlhlBtTmwVU3+zzvIuolFtAVa1JJcj5wLj0bCLZfkQNgWunwmpI= Received: (qmail 69102 invoked by alias); 23 Jun 2017 21:46:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 69086 invoked by uid 89); 23 Jun 2017 21:46:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=his X-HELO: mail-lf0-f47.google.com Received: from mail-lf0-f47.google.com (HELO mail-lf0-f47.google.com) (209.85.215.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 23 Jun 2017 21:46:13 +0000 Received: by mail-lf0-f47.google.com with SMTP id h22so37443107lfk.3 for ; Fri, 23 Jun 2017 14:46:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Wq8DjepXGuicRDm6LQt9VgwViLTyh8EHc+X0w9gPMLE=; b=Jb6Q7yzccntgb26pdSbqvUQpi7P5YUpUo4U3RvkFLBs3GAL2Q+0BEt0laakZD4UBw6 TzmhFUuz/sWWqX2sCYJgpMargcOvjNGkKfjN5QJKJZoG3/p9BPyu7YHmsrTI/CNOyVer 4XDNPONlFHW4ZDQXrWxrLGyI37NNaGDUhQhGXFaP9liimq04eBBVf2lM/TW1QIP+FL9Y 1B0ogctBTHWHC7NBBJ05cGGoHOr9GDvns+DRHCXR8AsiuDYS9jA0XHQ5LePu8N5RdpvN PseAGAREhr7H8+7Ix7n4TZS7efYHNkXv3fdOyEMXAvmdQNmcTAV9l7Labl9KaS8o8oiZ 4J/g== X-Gm-Message-State: AKS2vOy21OgjJXn9nnK2/yppYEBloaN2sVKTEWBOr+faclOKP8SJtvNP evP6I1uNQ6l7TCOTyhdC/a6ikIeX77Db X-Received: by 10.46.84.28 with SMTP id i28mr3031471ljb.44.1498254371290; Fri, 23 Jun 2017 14:46:11 -0700 (PDT) MIME-Version: 1.0 Received: by 10.25.158.3 with HTTP; Fri, 23 Jun 2017 14:46:10 -0700 (PDT) In-Reply-To: <20170612104000.GA38916@arm.com> References: <6ebb24ef-0912-cf5f-74a4-b4acd372dbf4@arm.com> <8a59f4fc-5450-ff42-aabd-bb32da42cd89@arm.com> <20170612104000.GA38916@arm.com> From: Jim Wilson Date: Fri, 23 Jun 2017 14:46:10 -0700 Message-ID: Subject: Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx To: James Greenhalgh Cc: "Richard Earnshaw (lists)" , "gcc-patches@gcc.gnu.org" , nd On Mon, Jun 12, 2017 at 3:40 AM, James Greenhalgh wrote: > In both the original patch, and the backport, you're modifying the > AArch64 options here. I'd expect the edits to be to the AArch32 options > (these start somewhere around line 15,000). Yes, I screwed this up. Richard Earnshaw already fixed the ARM Option list in one of his -mcpu patches. I checked in a fix for the AArch64 Option list under the obvious rule. Tested with a make doc, and using info to look at the docs to make sure that they are right. I will fix the gcc-7 backport before I check it in. Jim gcc/ * doc/invoke.texi (AArch64 Options, -mtune): Re-add falkor and qdf24xx. Index: doc/invoke.texi =================================================================== --- doc/invoke.texi (revision 249611) +++ doc/invoke.texi (working copy) @@ -14079,7 +14079,8 @@ Specify the name of the target processor for which performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{exynos-m1}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, +@samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},