From patchwork Tue Oct 13 08:46:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 1381405 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=aXMrtuQO; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C9Tl20HQvz9sTs for ; Tue, 13 Oct 2020 19:50:04 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 566F138708BE; Tue, 13 Oct 2020 08:50:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 566F138708BE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1602579001; bh=XyhWEm5DQlRSLuNv8+WQwfDvxCmjmAeJmGlr1fuq4Bo=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=aXMrtuQOfoE/+/u1ij1wTNW79om4cl9xOnDN7aRalokwkj+BI5iaD5p+BmIselSEH jDtn9eFIRopv92GyEwvu7p1hLTjQ0y94+iz4e/DHIBPNCtCEHqPFDVtlm2Senoz+2u B236ESDozMjeGMwnApwjxF5SO2Qm2aJftwJF2bt8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id ABA5F3857003 for ; Tue, 13 Oct 2020 08:49:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org ABA5F3857003 Received: by mail-wr1-x436.google.com with SMTP id n15so23009072wrq.2 for ; Tue, 13 Oct 2020 01:49:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=3Lf1d82TrGqH4OLKU5fVMR9R0hxoB3cFcSB1zC7wo0Q=; b=L9XE8mzXchi+ASH58UYP+3cUPnMtke6DxiVxfcYhLzzqT2pbLFYrBJb1xUNZxtaB92 GdBzkz45ixdR61N7TJW48lSoqKmp1Vzfs0SS7VFhT65+x7LHjx/Q7UHYDx6OB+ZgRVmW aYSk2JH5MTZwH7Rf4+wlIq/K7t6l3ib/09+uQI1nOfAvz9oo2vlJR1FFerLgSLibzb6S ok84ju1ApXVZNWQtn+7ciPzZ3824Jqsh2g5KiU+WBYtF3Edc/4RyXxQWjtlWrArr08sr zfs4QgHfd/yNFqWGfTezesCglXM4v5WPKO1ASEjfRC1UsbZgiclR2YIvaAPXDSbaNnCz Rc4A== X-Gm-Message-State: AOAM530rZCpqRgqUAqKqaNcAAWe7J5GG053aen5cpPYEWv0vxWf68qth aOii2en8AbqKQVTzB0tryF3SoSPXalFnniA87St4sXV3O1H6OA== X-Google-Smtp-Source: ABdhPJyzl3HvnZSM1OZlgGCfo1auKlHOgEcRj1y6SkE3OgxmQAzOWaPkvv8okOxr8nNjf571Z2pP3zJurKgnVKSaGfk= X-Received: by 2002:adf:f1c1:: with SMTP id z1mr10306318wro.331.1602578996534; Tue, 13 Oct 2020 01:49:56 -0700 (PDT) MIME-Version: 1.0 Date: Tue, 13 Oct 2020 16:46:13 +0800 Message-ID: Subject: [Patch] x86: Enable GCC support for Intel Hreset extension To: GCC Patches , Kirill Yukhin , Uros Bizjak X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hongyu Wang via Gcc-patches From: Hongyu Wang Reply-To: Hongyu Wang Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi: This patch is about to support Intel Hreset instruction. Hreset provides a hint to the processor to selectively reset the prediction history of the current logical processor. For more details, please refer to https://software.intel.com/content/dam/develop/external/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf Bootstrap ok, regression test on i386/x86 backend is ok. OK for master? gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect HRESET. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET, OPTION_MASK_ISA2_HRESET_UNSET): New macros. (ix86_handle_option): Handle -mhreset. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_HRESET. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for hreset. * config.gcc: Add hresetintrin.h * config/i386/hresetintrin.h: New header file. * config/i386/x86gprintrin.h: Include hresetintrin.h. * config/i386/cpuid.h (bit_HRESET): New. * config/i386/i386-builtin.def: Add new builtin. * config/i386/i386-expand.c (ix86_expand_builtin): Handle new builtin. * config/i386/i386-c.c (ix86_target_macros_internal): Define __HRESET__. * config/i386/i386-options.c (isa2_opts): Add -mhreset. (ix86_valid_target_attribute_inner_p): Handle hreset. * config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P, PTA_HRESET): New. (PTA_ALDERLAKE): Add PTA_HRESET. * config/i386/i386.opt: Add option -mhreset. * config/i386/i386.md (UNSPECV_HRESET): New unspec. (hreset): New define_insn. * doc/invoke.texi: Document -mhreset. * doc/extend.texi: Document hreset. gcc/testsuite/ * gcc.target/i386/hreset-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Update -mhreset. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. * g++.dg/other/i386-2.C: Likewise. * g++.dg/other/i386-3.C: Likewise. From 9dbb6bfb28431cd52149e12cc5f359be7fb46c64 Mon Sep 17 00:00:00 2001 From: Hongyu Wang Date: Tue, 7 Apr 2020 18:39:53 +0000 Subject: [PATCH] Enable Intel HRESET Instruction gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect HRESET. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET, OPTION_MASK_ISA2_HRESET_UNSET): New macros. (ix86_handle_option): Handle -mhreset. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_HRESET. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for hreset. * config.gcc: Add hresetintrin.h * config/i386/hresetintrin.h: New header file. * config/i386/x86gprintrin.h: Include hresetintrin.h. * config/i386/cpuid.h (bit_HRESET): New. * config/i386/i386-builtin.def: Add new builtin. * config/i386/i386-expand.c (ix86_expand_builtin): Handle new builtin. * config/i386/i386-c.c (ix86_target_macros_internal): Define __HRESET__. * config/i386/i386-options.c (isa2_opts): Add -mhreset. (ix86_valid_target_attribute_inner_p): Handle hreset. * config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P, PTA_HRESET): New. (PTA_ALDERLAKE): Add PTA_HRESET. * config/i386/i386.opt: Add option -mhreset. * config/i386/i386.md (UNSPECV_HRESET): New unspec. (hreset): New define_insn. * doc/invoke.texi: Document -mhreset. * doc/extend.texi: Document hreset. gcc/testsuite/ * gcc.target/i386/hreset-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Update -mhreset. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. * g++.dg/other/i386-2.C: Likewise. * g++.dg/other/i386-3.C: Likewise. --- gcc/common/config/i386/cpuinfo.h | 3 ++ gcc/common/config/i386/i386-common.c | 15 ++++++ gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + gcc/config.gcc | 4 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/hresetintrin.h | 53 +++++++++++++++++++ gcc/config/i386/i386-builtin.def | 3 ++ gcc/config/i386/i386-c.c | 3 +- gcc/config/i386/i386-expand.c | 8 +++ gcc/config/i386/i386-options.c | 4 +- gcc/config/i386/i386.h | 5 +- gcc/config/i386/i386.md | 11 ++++ gcc/config/i386/i386.opt | 4 ++ gcc/config/i386/x86gprintrin.h | 2 + gcc/doc/extend.texi | 5 ++ gcc/doc/invoke.texi | 9 ++-- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/hreset-1.c | 11 ++++ 19 files changed, 137 insertions(+), 8 deletions(-) create mode 100644 gcc/config/i386/hresetintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/hreset-1.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index c96455ce64f..c9ff7c94e6c 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -705,6 +705,9 @@ get_available_features (struct __processor_model *cpu_model, __cpuid_count (7, 1, eax, ebx, ecx, edx); if (eax & bit_AVX512BF16) set_feature (FEATURE_AVX512BF16); + if (eax & bit_HRESET) + set_feature (FEATURE_HRESET); + } } diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 62a620b4430..5b5ccc7a279 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -163,6 +163,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK +#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -254,6 +255,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 +#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -702,6 +704,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mhreset: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET; + } + return true; + case OPT_mavx5124fmaps: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 5b94b1f1df7..2acef3c4689 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -219,6 +219,7 @@ enum processor_features FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16, + FEATURE_HRESET, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 3c830ea08ff..1c3fde0ea39 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -163,4 +163,5 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("amx-tile", FEATURE_AMX_TILE, P_NONE, "-mamx-tile") ISA_NAMES_TABLE_ENTRY("amx-int8", FEATURE_AMX_INT8, P_NONE, "-mamx-int8") ISA_NAMES_TABLE_ENTRY("amx-bf16", FEATURE_AMX_BF16, P_NONE, "-mamx-bf16") + ISA_NAMES_TABLE_ENTRY("hreset", FEATURE_HRESET, P_NONE, "-mhreset") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index d5634b043e2..2225b75f1dd 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -413,7 +413,7 @@ i[34567]86-*-*) avx512bf16intrin.h enqcmdintrin.h serializeintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h tsxldtrkintrin.h amxtileintrin.h amxint8intrin.h - amxbf16intrin.h x86gprintrin.h" + amxbf16intrin.h x86gprintrin.h hresetintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -449,7 +449,7 @@ x86_64-*-*) avx512bf16intrin.h enqcmdintrin.h serializeintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h tsxldtrkintrin.h amxtileintrin.h amxint8intrin.h - amxbf16intrin.h x86gprintrin.h" + amxbf16intrin.h x86gprintrin.h hresetintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 4598434fd02..aded619b758 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -26,6 +26,7 @@ /* %eax */ #define bit_AVX512BF16 (1 << 5) +#define bit_HRESET (1 << 22) /* %ecx */ #define bit_SSE3 (1 << 0) diff --git a/gcc/config/i386/hresetintrin.h b/gcc/config/i386/hresetintrin.h new file mode 100644 index 00000000000..2aeb221d765 --- /dev/null +++ b/gcc/config/i386/hresetintrin.h @@ -0,0 +1,53 @@ +/* Copyright (C) 2020 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#if !defined _X86GPRINTRIN_H_INCLUDED +# error "Never use directly; include instead." +#endif + +#ifndef _HRESETINTRIN_H_INCLUDED +#define _HRESETINTRIN_H_INCLUDED + +#ifndef __HRESET__ +#pragma GCC push_options +#pragma GCC target ("hreset") +#define __DISABLE_HRESET__ +#endif /* __HRESET__ */ + +#ifdef __OPTIMIZE__ +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_hreset (unsigned int __EAX) +{ + __builtin_ia32_hreset (__EAX); +} +#else +#define _hreset(EAX) \ + (__builtin_ia32_hreset (EAX)) +#endif + +#ifdef __DISABLE_HRESET__ +#undef __DISABLE_HRESET__ +#pragma GCC pop_options +#endif /* __DISABLE_HRESET__ */ +#endif /* _HRESETINTRIN_H_INCLUDED. */ diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index fec5cef0b55..0e8b5e6ef6b 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -452,6 +452,9 @@ BDESC (0, OPTION_MASK_ISA2_SERIALIZE, CODE_FOR_serialize, "__builtin_ia32_serial BDESC (0, OPTION_MASK_ISA2_TSXLDTRK, CODE_FOR_xsusldtrk, "__builtin_ia32_xsusldtrk", IX86_BUILTIN_XSUSLDTRK, UNKNOWN, (int) VOID_FTYPE_VOID) BDESC (0, OPTION_MASK_ISA2_TSXLDTRK, CODE_FOR_xresldtrk, "__builtin_ia32_xresldtrk", IX86_BUILTIN_XRESLDTRK, UNKNOWN, (int) VOID_FTYPE_VOID) +/* HRESET */ +BDESC (0, OPTION_MASK_ISA2_HRESET, CODE_FOR_hreset, "__builtin_ia32_hreset", IX86_BUILTIN_HRESET, UNKNOWN, (int) VOID_FTYPE_UNSIGNED) + BDESC_END (SPECIAL_ARGS, ARGS) /* Builtins with variable number of arguments. */ diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index e647fce9ad4..b8680b4a67e 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -598,7 +598,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__LAHF_SAHF__"); if (isa_flag2 & OPTION_MASK_ISA2_MOVBE) def_or_undef (parse_in, "__MOVBE__"); - + if (isa_flag2 & OPTION_MASK_ISA2_HRESET) + def_or_undef (parse_in, "__HRESET__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index e6f8b314f18..b797b149edd 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -12807,6 +12807,14 @@ rdseed_step: emit_insn (gen_incssp (mode, op0)); return 0; + case IX86_BUILTIN_HRESET: + icode = CODE_FOR_hreset; + arg0 = CALL_EXPR_ARG (exp, 0); + op0 = expand_normal (arg0); + op0 = force_reg (SImode, op0); + emit_insn (gen_hreset (op0)); + return 0; + case IX86_BUILTIN_RSTORSSP: case IX86_BUILTIN_CLRSSBSY: arg0 = CALL_EXPR_ARG (exp, 0); diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index a59bd703880..c97d30c3fb9 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -212,7 +212,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mtsxldtrk", OPTION_MASK_ISA2_TSXLDTRK }, { "-mamx-tile", OPTION_MASK_ISA2_AMX_TILE }, { "-mamx-int8", OPTION_MASK_ISA2_AMX_INT8 }, - { "-mamx-bf16", OPTION_MASK_ISA2_AMX_BF16 } + { "-mamx-bf16", OPTION_MASK_ISA2_AMX_BF16 }, + { "-mhreset", OPTION_MASK_ISA2_HRESET } }; static struct ix86_target_opts isa_opts[] = { @@ -1039,6 +1040,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("amx-tile", OPT_mamx_tile), IX86_ATTR_ISA ("amx-int8", OPT_mamx_int8), IX86_ATTR_ISA ("amx-bf16", OPT_mamx_bf16), + IX86_ATTR_ISA ("hreset", OPT_mhreset), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 9a5de6a0e9c..8643dd600a1 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -209,6 +209,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_AMX_INT8_P(x) TARGET_ISA2_AMX_INT8(x) #define TARGET_AMX_BF16 TARGET_ISA2_AMX_BF16 #define TARGET_AMX_BF16_P(x) TARGET_ISA2_AMX_BF16(x) +#define TARGET_HRESET TARGET_ISA2_HRESET +#define TARGET_HRESET_P(x) TARGET_ISA2_HRESET_P(x) #define TARGET_LP64 TARGET_ABI_64 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) @@ -2475,6 +2477,7 @@ const wide_int_bitmask PTA_TSXLDTRK (0, HOST_WIDE_INT_1U << 18); const wide_int_bitmask PTA_AMX_TILE(0, HOST_WIDE_INT_1U << 19); const wide_int_bitmask PTA_AMX_INT8(0, HOST_WIDE_INT_1U << 20); const wide_int_bitmask PTA_AMX_BF16(0, HOST_WIDE_INT_1U << 21); +const wide_int_bitmask PTA_HRESET(0, HOST_WIDE_INT_1U << 22); const wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR; @@ -2520,7 +2523,7 @@ const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16; const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE - | PTA_WAITPKG | PTA_SERIALIZE; + | PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9dd12cf8643..be5fd7b0ec3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -310,6 +310,9 @@ ;; For patchable area support UNSPECV_PATCHABLE_AREA + + ;; For HRESET support + UNSPECV_HRESET ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -21655,6 +21658,14 @@ (set_attr "length_immediate" "0") (set_attr "modrm" "0")]) +(define_insn "hreset" + [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")] + UNSPECV_HRESET)] + "TARGET_HRESET" + "hreset\t{$0|0}" + [(set_attr "type" "other") + (set_attr "length" "4")]) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 9389dc24948..a0f28eedf11 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1127,3 +1127,7 @@ Support AMX-INT8 built-in functions and code generation. mamx-bf16 Target Report Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save Support AMX-BF16 built-in functions and code generation. + +mhreset +Target Report Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save +Support HRESET built-in functions and code generation. diff --git a/gcc/config/i386/x86gprintrin.h b/gcc/config/i386/x86gprintrin.h index ecfb1c0e67f..e0558528a63 100644 --- a/gcc/config/i386/x86gprintrin.h +++ b/gcc/config/i386/x86gprintrin.h @@ -90,6 +90,8 @@ #include +#include + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _wbinvd (void) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b9684dc7a06..14dcf219d75 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6638,6 +6638,11 @@ Enable/disable the generation of the AMX-INT8 instructions. @cindex @code{target("amx-bf16")} function attribute, x86 Enable/disable the generation of the AMX-BF16 instructions. +@item hreset +@itemx no-hreset +@cindex @code{target("hreset")} function attribute, x86 +Enable/disable the generation of the HRESET instruction. + @item cld @itemx no-cld @cindex @code{target("cld")} function attribute, x86 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b8c807e631c..dc9b8828648 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1361,7 +1361,7 @@ See RS/6000 and PowerPC Options. -mshstk -mmanual-endbr -mforce-indirect-call -mavx512vbmi2 -mavx512bf16 -menqcmd @gol -mvpclmulqdq -mavx512bitalg -mmovdiri -mmovdir64b -mavx512vpopcntdq @gol -mavx5124fmaps -mavx512vnni -mavx5124vnniw -mprfchw -mrdpid @gol --mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol +-mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk -mhreset@gol -mamx-tile -mamx-int8 -mamx-bf16@gol -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol @@ -30261,6 +30261,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @itemx -mamx-bf16 @opindex mamx-bf16 +@need 200 +@itemx -mhreset +@opindex mhreset These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, @@ -30269,8 +30272,8 @@ WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP, 3DNow!@:, enhanced 3DNow!@:, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE, XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2, GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, -ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE -or CLDEMOTE extended instruction sets. Each has a corresponding +ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, +HRESET or CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-} option to disable use of these instructions. These extensions are also available as built-in functions: see diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 8e669f12215..df7524e6b4d 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -74,6 +74,7 @@ extern void test_avx512vp2intersect (void) __attribute__((__target__("avx512vp2i extern void test_amx_tile (void) __attribute__((__target__("amx-tile"))); extern void test_amx_int8 (void) __attribute__((__target__("amx-int8"))); extern void test_amx_bf16 (void) __attribute__((__target__("amx-bf16"))); +extern void test_hreset (void) __attribute__((__target__("hreset"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -149,6 +150,7 @@ extern void test_no_avx512vp2intersect (void) __attribute__((__target__("no-avx5 extern void test_no_amx_tile (void) __attribute__((__target__("no-amx-tile"))); extern void test_no_amx_int8 (void) __attribute__((__target__("no-amx-int8"))); extern void test_no_amx_bf16 (void) __attribute__((__target__("no-amx-bf16"))); +extern void test_no_hreset (void) __attribute__((__target__("no-hreset"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/hreset-1.c b/gcc/testsuite/gcc.target/i386/hreset-1.c new file mode 100644 index 00000000000..573513f8c58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/hreset-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mhreset" } */ +/* { dg-final { scan-assembler-times "eax" 1 } } */ +/* { dg-final { scan-assembler-times "hreset\[ \\t\]+\[\$\]\?0" 1 } } */ + +#include + +void foo(unsigned int eax) +{ + _hreset (eax); +} -- 2.25.1