From patchwork Wed Dec 7 19:15:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 130018 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 9FA471007D1 for ; Thu, 8 Dec 2011 06:15:48 +1100 (EST) Received: (qmail 6234 invoked by alias); 7 Dec 2011 19:15:46 -0000 Received: (qmail 6221 invoked by uid 22791); 7 Dec 2011 19:15:43 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_MG X-Spam-Check-By: sourceware.org Received: from mail-vw0-f47.google.com (HELO mail-vw0-f47.google.com) (209.85.212.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 07 Dec 2011 19:15:29 +0000 Received: by vbbfc21 with SMTP id fc21so791358vbb.20 for ; Wed, 07 Dec 2011 11:15:29 -0800 (PST) MIME-Version: 1.0 Received: by 10.52.33.69 with SMTP id p5mr11722612vdi.78.1323285329071; Wed, 07 Dec 2011 11:15:29 -0800 (PST) Received: by 10.220.229.66 with HTTP; Wed, 7 Dec 2011 11:15:29 -0800 (PST) In-Reply-To: References: Date: Wed, 7 Dec 2011 11:15:29 -0800 Message-ID: Subject: Re: [PATCH] [MIPS] Add -march=octeon+ support for GCC From: Andrew Pinski To: GCC Patches , Richard Sandiford X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Tue, Dec 6, 2011 at 6:28 PM, Andrew Pinski wrote: > Hi, >  This patch adds -march=octeon+ to GCC. > OK? Bootstrapped and tested on mips64-linux-gnu configured with > --with-arch=octeon+ . > > Thanks, > Andrew Pinski > > gcc/ChangeLog: > * mips/mips-cpus.def (octeon+): New CPU. > * config/mips/mips-tables.opt: Regenerate. > * config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'. > > testsuite/ChangeLog: > * gcc.target/mips/mult-1.c: Forbit all Octeon processors. > * gcc.target/mips/dmult-1.c: Likewise. > * gcc.target/mips/branch-1.c: Likewise. > * gcc.target/mips/extend-1.c: Likewise. Woops I forgot the patch. Thanks, Andrew Pinski Index: testsuite/gcc.target/mips/mult-1.c =================================================================== --- testsuite/gcc.target/mips/mult-1.c (revision 182066) +++ testsuite/gcc.target/mips/mult-1.c (working copy) @@ -1,6 +1,6 @@ /* For SI->DI widening multiplication we should use DINS to combine the two halves. For Octeon use DMUL with explicit widening. */ -/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */ +/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon\[\+0-9\]*" } */ /* { dg-final { scan-assembler "\tdins\t" } } */ /* { dg-final { scan-assembler-not "\tdsll\t" } } */ /* { dg-final { scan-assembler-not "\tdsrl\t" } } */ Index: testsuite/gcc.target/mips/dmult-1.c =================================================================== --- testsuite/gcc.target/mips/dmult-1.c (revision 182066) +++ testsuite/gcc.target/mips/dmult-1.c (working copy) @@ -1,4 +1,4 @@ -/* { dg-options "forbid_cpu=octeon -mgp64" } */ +/* { dg-options "forbid_cpu=octeon\[\+0-9\]* -mgp64" } */ /* { dg-final { scan-assembler "\tdmult\t" } } */ /* { dg-final { scan-assembler "\tmflo\t" } } */ /* { dg-final { scan-assembler-not "\tdmul\t" } } */ Index: testsuite/gcc.target/mips/branch-1.c =================================================================== --- testsuite/gcc.target/mips/branch-1.c (revision 182066) +++ testsuite/gcc.target/mips/branch-1.c (working copy) @@ -2,7 +2,7 @@ but we test for "bbit" elsewhere. On other targets, we should implement the "if" statements using an "andi" instruction followed by a branch on zero. */ -/* { dg-options "-O2 forbid_cpu=octeon" } */ +/* { dg-options "-O2 forbid_cpu=octeon\[\+0-9\]*" } */ void bar (void); NOMIPS16 void f1 (int x) { if (x & 4) bar (); } Index: testsuite/gcc.target/mips/extend-1.c =================================================================== --- testsuite/gcc.target/mips/extend-1.c (revision 182066) +++ testsuite/gcc.target/mips/extend-1.c (working copy) @@ -1,4 +1,4 @@ -/* { dg-options "-O -mgp64 forbid_cpu=octeon" } */ +/* { dg-options "-O -mgp64 forbid_cpu=octeon\[\+0-9\]*" } */ /* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */ /* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */ /* { dg-final { scan-assembler-not "\tsll\t" } } */ Index: config/mips/mips-tables.opt =================================================================== --- config/mips/mips-tables.opt (revision 182066) +++ config/mips/mips-tables.opt (working copy) @@ -603,3 +603,6 @@ EnumValue Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical +EnumValue +Enum(mips_arch_opt_value) String(octeon+) Value(81) Canonical + Index: config/mips/mips-cpus.def =================================================================== --- config/mips/mips-cpus.def (revision 182066) +++ config/mips/mips-cpus.def (working copy) @@ -145,3 +145,4 @@ /* MIPS64 Release 2 processors. */ MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) Index: config/mips/mips.h =================================================================== --- config/mips/mips.h (revision 182066) +++ config/mips/mips.h (working copy) @@ -329,7 +329,10 @@ \ macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ for (p = macro; *p != 0; p++) \ - *p = TOUPPER (*p); \ + if (*p == '+') \ + *p = 'P'; \ + else \ + *p = TOUPPER (*p); \ \ builtin_define (macro); \ builtin_define_with_value ((PREFIX), (INFO)->name, 1); \