| Message ID | CA+=Sn1=_LW-oH+_6mahtKaGxaK8oKbjAWNShVXNaRYUdQ1XhKw@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
On Fri, Aug 18, 2017 at 12:17 PM Andrew Pinski <pinskia@gmail.com> wrote: > > Like https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00060.html for > PowerPC, we should do something similar for aarch64. This pattern > does show up in SPEC CPU 2006 in astar but I did not look into > performance improvement of it though. > > OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions. Ping? It has been over a year and half now. > > Thanks, > Andrew Pinski > > ChangeLog: > * config/aarch64/aarch64.md (*frintz): New pattern. > > testsuite/ChangeLog: > * testsuite/gcc.target/aarch64/floattointtofloat-1.c: New testcase.
On Fri, Aug 18, 2017 at 12:17 PM Andrew Pinski <pinskia@gmail.com> wrote: > > Like https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00060.html for > PowerPC, we should do something similar for aarch64. This pattern > does show up in SPEC CPU 2006 in astar but I did not look into > performance improvement of it though. > > OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions. Ping? I has been over 2 years now too. Thanks, Andrew > > Thanks, > Andrew Pinski > > ChangeLog: > * config/aarch64/aarch64.md (*frintz): New pattern. > > testsuite/ChangeLog: > * testsuite/gcc.target/aarch64/floattointtofloat-1.c: New testcase.
Andrew Pinski <pinskia@gmail.com> writes: > On Fri, Aug 18, 2017 at 12:17 PM Andrew Pinski <pinskia@gmail.com> wrote: >> >> Like https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00060.html for >> PowerPC, we should do something similar for aarch64. This pattern >> does show up in SPEC CPU 2006 in astar but I did not look into >> performance improvement of it though. >> >> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions. > > Ping? I has been over 2 years now too. I think it'd better to do this in match.pd, folding to IFN_TRUNC. The rule will then automatically check whether the target supports IFN_TRUNC/btrunc_optab for the required mode. Thanks, Richard
On Tue, Nov 26, 2019 at 2:30 PM Richard Sandiford <richard.sandiford@arm.com> wrote: > > Andrew Pinski <pinskia@gmail.com> writes: > > On Fri, Aug 18, 2017 at 12:17 PM Andrew Pinski <pinskia@gmail.com> wrote: > >> > >> Like https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00060.html for > >> PowerPC, we should do something similar for aarch64. This pattern > >> does show up in SPEC CPU 2006 in astar but I did not look into > >> performance improvement of it though. > >> > >> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions. > > > > Ping? I has been over 2 years now too. > > I think it'd better to do this in match.pd, folding to IFN_TRUNC. > The rule will then automatically check whether the target supports > IFN_TRUNC/btrunc_optab for the required mode. Yes I agree, it should be done generically. I will look into doing that for stage 1. Thanks, Andrew > > Thanks, > Richard
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5e6b027..1439bd0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4645,6 +4645,16 @@ [(set_attr "type" "f_cvti2f")] ) +(define_insn "*frintz" + [(set (match_operand:GPF 0 "register_operand" "=w") + (float:GPF (fix:GPI (match_operand:GPF 1 "register_operand" "w"))))] + "TARGET_FLOAT && flag_unsafe_math_optimizations && !flag_trapping_math" + "frintz %<GPF:s>0, %<GPF:s>1" + [(set_attr "simd" "yes") + (set_attr "fp" "no") + (set_attr "type" "neon_int_to_fp_<Vetype>")] +) + ;; If we do not have ARMv8.2-A 16-bit floating point extensions, the ;; midend will arrange for an SImode conversion to HFmode to first go ;; through DFmode, then to HFmode. But first it will try converting diff --git a/gcc/testsuite/gcc.target/aarch64/floattointtofloat-1.c b/gcc/testsuite/gcc.target/aarch64/floattointtofloat-1.c new file mode 100644 index 0000000..c1209c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/floattointtofloat-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast" } */ +double dll(double a) +{ + return (long long)a; +} +double di(double a) +{ + return (int)a; +} +float fll(float a) +{ + return (long long)a; +} +float fi(float a) +{ + return (int)a; +} +/* { dg-final { scan-assembler-times "frintz" 4 } } */ +
Like https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00060.html for PowerPC, we should do something similar for aarch64. This pattern does show up in SPEC CPU 2006 in astar but I did not look into performance improvement of it though. OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions. Thanks, Andrew Pinski ChangeLog: * config/aarch64/aarch64.md (*frintz): New pattern. testsuite/ChangeLog: * testsuite/gcc.target/aarch64/floattointtofloat-1.c: New testcase. commit 9cef5e196729df5a197b81b72192d687683a057a Author: Andrew Pinski <apinski@cavium.com> Date: Thu Aug 17 22:31:15 2017 -0700 Fix 19869: (double)(long)double_var could be better optimized Use FRINTZ to optimize this. Signed-off-by: Andrew Pinski <apinski@cavium.com>