From patchwork Tue Dec 28 17:07:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Koning X-Patchwork-Id: 76850 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 17559B70AF for ; Wed, 29 Dec 2010 04:08:11 +1100 (EST) Received: (qmail 29029 invoked by alias); 28 Dec 2010 17:08:07 -0000 Received: (qmail 29021 invoked by uid 22791); 28 Dec 2010 17:08:05 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL, BAYES_05, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from ausc60ps301.us.dell.com (HELO ausc60ps301.us.dell.com) (143.166.148.206) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 28 Dec 2010 17:07:59 +0000 X-Loopcount0: from 10.152.240.141 From: Paul Koning Subject: [PATCH] pdp11: correct length for float literal case Date: Tue, 28 Dec 2010 12:07:48 -0500 Message-Id: To: gcc-patches Mime-Version: 1.0 (Apple Message framework v1082) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org In the pdp11, float literal instruction operands are one word long even though float normally is 2 or 4 words. The code generation handles this correctly but the length attributes were wrong. This patch corrects that. Tested with build and make check. Committed. paul ChangeLog: 2010-12-28 Paul Koning * config/pdp11/pdp11.md: Correct length attribute for float literal case. Index: config/pdp11/pdp11.md =================================================================== --- config/pdp11/pdp11.md (revision 168294) +++ config/pdp11/pdp11.md (working copy) @@ -98,9 +98,9 @@ (define_asm_attributes [(set_attr "type" "unknown") ; length for asm is the max length per statement. That would be -; 5 words, for a floating point instruction with a literal constant -; argument. - (set_attr "length" "10")]) +; 3 words, for a two-operand instruction with extra word addressing +; modes for both operands. + (set_attr "length" "6")]) ;; define function units @@ -114,8 +114,8 @@ ;; compare (define_insn "*cmpdf" [(set (cc0) - (compare (match_operand:DF 0 "general_operand" "fR,fR,Q,Q,F") - (match_operand:DF 1 "register_or_const0_operand" "G,a,G,a,a")))] + (compare (match_operand:DF 0 "general_operand" "fR,fR,Q,QF") + (match_operand:DF 1 "register_or_const0_operand" "G,a,G,a")))] "TARGET_FPU" "* { @@ -125,7 +125,7 @@ else return \"{cmpd|cmpf} %0, %1\;cfcc\"; }" - [(set_attr "length" "4,4,6,6,12")]) + [(set_attr "length" "4,4,6,6")]) (define_insn "*cmp" [(set (cc0) @@ -291,7 +291,7 @@ (define_insn "movdf" [(set (match_operand:DF 0 "float_nonimm_operand" "=a,fR,a,Q,g") - (match_operand:DF 1 "float_operand" "fFR,a,Q,a,g"))] + (match_operand:DF 1 "float_operand" "fR,a,FQ,a,g"))] "TARGET_FPU" "* if (which_alternative ==0 || which_alternative == 2) return \"ldd %1, %0\"; @@ -299,12 +299,12 @@ return \"std %1, %0\"; else return output_move_multiple (operands); " -;; just a guess.. - [(set_attr "length" "2,2,10,10,32")]) +;; last one is worst-case + [(set_attr "length" "2,2,4,4,24")]) (define_insn "movsf" [(set (match_operand:SF 0 "float_nonimm_operand" "=a,fR,a,Q,g") - (match_operand:SF 1 "float_operand" "fFR,a,Q,a,g"))] + (match_operand:SF 1 "float_operand" "fR,a,FQ,a,g"))] "TARGET_FPU" "* if (which_alternative ==0 || which_alternative == 2) return \"{ldcfd|movof} %1, %0\"; @@ -312,8 +312,8 @@ return \"{stcdf|movfo} %1, %0\"; else return output_move_multiple (operands); " -;; just a guess.. - [(set_attr "length" "2,2,10,10,16")]) +;; last one is worst-case + [(set_attr "length" "2,2,4,4,12")]) ;; maybe fiddle a bit with move_ratio, then ;; let constraints only accept a register ... @@ -607,12 +607,12 @@ ;;- add instructions (define_insn "adddf3" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (plus:DF (match_operand:DF 1 "register_operand" "%0,0,0") - (match_operand:DF 2 "general_operand" "fR,Q,F")))] + [(set (match_operand:DF 0 "register_operand" "=a,a") + (plus:DF (match_operand:DF 1 "register_operand" "%0,0") + (match_operand:DF 2 "general_operand" "fR,QF")))] "TARGET_FPU" "{addd|addf} %2, %0" - [(set_attr "length" "2,4,10")]) + [(set_attr "length" "2,4")]) (define_insn "adddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,o") @@ -1261,12 +1261,12 @@ ;;- multiply (define_insn "muldf3" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (mult:DF (match_operand:DF 1 "register_operand" "%0,0,0") - (match_operand:DF 2 "float_operand" "fR,Q,F")))] + [(set (match_operand:DF 0 "register_operand" "=a,a") + (mult:DF (match_operand:DF 1 "register_operand" "%0,0") + (match_operand:DF 2 "float_operand" "fR,QF")))] "TARGET_FPU" "{muld|mulf} %2, %0" - [(set_attr "length" "2,4,10")]) + [(set_attr "length" "2,4")]) ;; 16 bit result multiply: ;; currently we multiply only into odd registers, so we don't use two @@ -1313,12 +1313,12 @@ ;;- divide (define_insn "divdf3" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (div:DF (match_operand:DF 1 "register_operand" "0,0,0") - (match_operand:DF 2 "general_operand" "fR,Q,F")))] + [(set (match_operand:DF 0 "register_operand" "=a,a") + (div:DF (match_operand:DF 1 "register_operand" "0,0") + (match_operand:DF 2 "general_operand" "fR,QF")))] "TARGET_FPU" "{divd|divf} %2, %0" - [(set_attr "length" "2,4,10")]) + [(set_attr "length" "2,4")]) (define_expand "divhi3"