From patchwork Mon Apr 18 14:17:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Carrot Wei X-Patchwork-Id: 91753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 76746B6F57 for ; Tue, 19 Apr 2011 00:18:33 +1000 (EST) Received: (qmail 20687 invoked by alias); 18 Apr 2011 14:18:32 -0000 Received: (qmail 20679 invoked by uid 22791); 18 Apr 2011 14:18:31 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_PASS, TW_QE, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (74.125.121.67) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 18 Apr 2011 14:17:46 +0000 Received: from kpbe12.cbf.corp.google.com (kpbe12.cbf.corp.google.com [172.25.105.76]) by smtp-out.google.com with ESMTP id p3IEHi1C016746 for ; Mon, 18 Apr 2011 07:17:44 -0700 Received: from ywg8 (ywg8.prod.google.com [10.192.7.8]) by kpbe12.cbf.corp.google.com with ESMTP id p3IEHgb1002599 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NOT) for ; Mon, 18 Apr 2011 07:17:43 -0700 Received: by ywg8 with SMTP id 8so1602890ywg.34 for ; Mon, 18 Apr 2011 07:17:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.134.34 with SMTP id l34mr4204664ybn.370.1303136262571; Mon, 18 Apr 2011 07:17:42 -0700 (PDT) Received: by 10.150.200.20 with HTTP; Mon, 18 Apr 2011 07:17:42 -0700 (PDT) In-Reply-To: <1303133594.17819.7.camel@e102346-lin.cambridge.arm.com> References: <4D9EE8C7.6030709@linaro.org> <1302874496.9717.198.camel@e102346-lin.cambridge.arm.com> <1303133594.17819.7.camel@e102346-lin.cambridge.arm.com> Date: Mon, 18 Apr 2011 22:17:42 +0800 Message-ID: Subject: Re: [PATCH, ARM] PR47855 Compute attr "length" for some thumb2 insns, 2/3 From: Carrot Wei To: Richard Earnshaw Cc: Ramana Radhakrishnan , gcc-patches@gcc.gnu.org X-System-Of-Record: true X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Mon, Apr 18, 2011 at 9:33 PM, Richard Earnshaw wrote: > > On Sat, 2011-04-16 at 12:34 +0800, Carrot Wei wrote: >> Hi Richard >> >> Thank you for the detailed explanation. It sounds like an inherent >> difficulty of rtl passes. Then the only opportunity is ldrb/strb >> instructions because they never affect cc registers. > > There are also some comparison operations that are also known to be 2 > bytes (because they are known to set the condition codes).  But yes, the > scope here is quite limited. > > R. So now this version only computes the correct length of ldrd/strb in insn arm_movqi_insn. Tested on arm qemu without regression. thanks Carrot ChangeLog: 2011-04-18 Wei Guozhi PR target/47855 * config/arm/arm-protos.h (thumb1_legitimate_address_p): New prototype. * config/arm/arm.c (thumb1_legitimate_address_p): Remove the static linkage. * config/arm/constraints.md (Uu): New constraint. * config/arm/arm.md (*arm_movqi_insn): Compute attr "length". Index: arm.c =================================================================== --- arm.c (revision 172353) +++ arm.c (working copy) @@ -5772,7 +5772,7 @@ thumb1_index_register_rtx_p (rtx x, int addresses based on the frame pointer or arg pointer until the reload pass starts. This is so that eliminating such addresses into stack based ones won't produce impossible code. */ -static int +int thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) { /* ??? Not clear if this is right. Experiment. */ Index: arm-protos.h =================================================================== --- arm-protos.h (revision 172353) +++ arm-protos.h (working copy) @@ -58,6 +58,7 @@ extern bool arm_legitimize_reload_addres int); extern rtx thumb_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); +extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int); extern int arm_const_double_rtx (rtx); extern int neg_const_double_rtx_ok_for_fpa (rtx); extern int vfp3_const_double_rtx (rtx); Index: constraints.md =================================================================== --- constraints.md (revision 172353) +++ constraints.md (working copy) @@ -36,6 +36,7 @@ ;; The following memory constraints have been used: ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us ;; in ARM state: Uq +;; in Thumb state: Uu (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS" @@ -332,6 +333,14 @@ (and (match_code "mem") (match_test "REG_P (XEXP (op, 0))"))) +(define_memory_constraint "Uu" + "@internal + In Thumb state an address that is valid in 16bit encoding." + (and (match_code "mem") + (match_test "TARGET_THUMB + && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0), + 0)"))) + ;; We used to have constraint letters for S and R in ARM state, but ;; all uses of these now appear to have been removed. Index: arm.md =================================================================== --- arm.md (revision 172353) +++ arm.md (working copy) @@ -5946,8 +5946,8 @@ (define_insn "*arm_movqi_insn" - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") - (match_operand:QI 1 "general_operand" "rI,K,m,r"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,l,Uu,r,m") + (match_operand:QI 1 "general_operand" "rI,K,Uu,l,m,r"))] "TARGET_32BIT && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" @@ -5955,10 +5955,14 @@ mov%?\\t%0, %1 mvn%?\\t%0, #%B1 ldr%(b%)\\t%0, %1 + str%(b%)\\t%1, %0 + ldr%(b%)\\t%0, %1 str%(b%)\\t%1, %0" - [(set_attr "type" "*,*,load1,store1") - (set_attr "insn" "mov,mvn,*,*") - (set_attr "predicable" "yes")] + [(set_attr "type" "*,*,load1,store1,load1,store1") + (set_attr "insn" "mov,mvn,*,*,*,*") + (set_attr "predicable" "yes") + (set_attr "arch" "any,any,t2,t2,any,any") + (set_attr "length" "4,4,2,2,4,4")] ) (define_insn "*thumb1_movqi_insn"