From patchwork Sat Apr 16 08:29:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 91481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D8893B6FE9 for ; Sat, 16 Apr 2011 18:29:56 +1000 (EST) Received: (qmail 6437 invoked by alias); 16 Apr 2011 08:29:54 -0000 Received: (qmail 6415 invoked by uid 22791); 16 Apr 2011 08:29:48 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST, TW_AV, TW_DD, TW_VD, TW_VN, TW_VX, TW_XV, TW_ZJ, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-px0-f176.google.com (HELO mail-px0-f176.google.com) (209.85.212.176) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 16 Apr 2011 08:29:15 +0000 Received: by pxi11 with SMTP id 11so7677920pxi.21 for ; Sat, 16 Apr 2011 01:29:15 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.209.10 with SMTP id h10mr1287169wfg.344.1302942555027; Sat, 16 Apr 2011 01:29:15 -0700 (PDT) Received: by 10.142.87.14 with HTTP; Sat, 16 Apr 2011 01:29:14 -0700 (PDT) Date: Sat, 16 Apr 2011 10:29:14 +0200 Message-ID: Subject: [PATCH 9/n, i386]: Merge SSE and AVX patterns using "enable" attribute. From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! Attached patch converts move patterns. 2011-04-15 Uros Bizjak * config/i386/sse.md (V16): New mode iterator. (VI1, VI8): Ditto. (AVXMODEQI, AVXMODEDI): Remove. (sse2, sse3): New mode attribute. (mov): Use V16 mode iterator. (*mov_internal): Merge with *avx_mov_internal. (push1): Use V16 mode iterator. (movmisalign): Ditto. (_movu): Merge from _movu and avx_movu. (*_movu): Merge from *_movu and *avx_movu. (_movdqu): Merge from sse2_movdqu and avx_movdqu. (*_movdqu): Merge from *sse2_movdqu and *avx_movdqu. (_lddqu) Merge from sse3_lddqu and avx_lddqu. (_movnt): Merge with avx_movnt. (_movnt): Merge from sse2_movntv2di and avx_movnt. * config/i386/i386.c (ix86_expand_vector_move_misalign): Update for renamed sse_movups, sse2_movupd and sse2_movdqu patterns. testsuite/ChangeLog: 2011-04-15 Uros Bizjak * gcc.target/i386/avx256-unaligned-load-1.c: Update scan patterns. * gcc.target/i386/avx256-unaligned-load-2.c: Ditto. * gcc.target/i386/avx256-unaligned-load-3.c: Ditto. * gcc.target/i386/avx256-unaligned-store-1.c: Ditto. * gcc.target/i386/avx256-unaligned-store-2.c: Ditto. * gcc.target/i386/avx256-unaligned-store-3.c: Ditto. Bootstrapped and regression tested on x86_64-pc-linux {,-m32} AVX target, committed to mainline SVN. Uros. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 172498) +++ config/i386/sse.md (working copy) @@ -18,6 +18,15 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +;; All vector modes including V1TImode. +(define_mode_iterator V16 + [(V32QI "TARGET_AVX") V16QI + (V16HI "TARGET_AVX") V8HI + (V8SI "TARGET_AVX") V4SI + (V4DI "TARGET_AVX") V2DI + V1TI + (V8SF "TARGET_AVX") V4SF + (V4DF "TARGET_AVX") V2DF]) ;; All vector float modes (define_mode_iterator VF @@ -43,6 +52,14 @@ (V8SI "TARGET_AVX") V4SI (V4DI "TARGET_AVX") V2DI]) +;; All QImode vector integer modes +(define_mode_iterator VI1 + [(V32QI "TARGET_AVX") V16QI]) + +;; All DImode vector integer modes +(define_mode_iterator VI8 + [(V4DI "TARGET_AVX") V2DI]) + ;; All 128bit vector integer modes (define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI]) @@ -59,22 +76,13 @@ ;; All 16-byte vector modes handled by SSE (define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF]) -(define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF]) ;; All 32-byte vector modes handled by AVX (define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF]) -;; All QI vector modes handled by AVX -(define_mode_iterator AVXMODEQI [V32QI V16QI]) - -;; All DI vector modes handled by AVX -(define_mode_iterator AVXMODEDI [V4DI V2DI]) - ;; All vector modes handled by AVX (define_mode_iterator AVXMODE [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF]) -(define_mode_iterator AVXMODE16 - [V16QI V8HI V4SI V2DI V1TI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF]) ;; Mix-n-match (define_mode_iterator SSEMODE124 [V16QI V8HI V4SI]) @@ -107,8 +115,8 @@ ;; Modes handled by storent patterns. (define_mode_iterator STORENT_MODE [(SF "TARGET_SSE4A") (DF "TARGET_SSE4A") - (SI "TARGET_SSE2") (V2DI "TARGET_SSE2") (V2DF "TARGET_SSE2") - (V4SF "TARGET_SSE") + (SI "TARGET_SSE2") (V2DI "TARGET_SSE2") + (V4SF "TARGET_SSE") (V2DF "TARGET_SSE2") (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")]) ;; Modes handled by vector extract patterns. @@ -124,6 +132,13 @@ (V4SF "sse") (V2DF "sse2") (V8SF "avx") (V4DF "avx")]) +(define_mode_attr sse2 + [(V16QI "sse2") (V32QI "avx") + (V2DI "sse2") (V4DI "avx")]) + +(define_mode_attr sse3 + [(V16QI "sse3") (V32QI "avx")]) + (define_mode_attr sse4_1 [(V4SF "sse4_1") (V2DF "sse4_1") (V8SF "avx") (V4DF "avx")]) @@ -192,19 +207,22 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; All of these patterns are enabled for SSE1 as well as SSE2. +;; This is essential for maintaining stable calling conventions. + (define_expand "mov" - [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "") - (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))] - "TARGET_AVX" + [(set (match_operand:V16 0 "nonimmediate_operand" "") + (match_operand:V16 1 "nonimmediate_operand" ""))] + "TARGET_SSE" { ix86_expand_vector_move (mode, operands); DONE; }) -(define_insn "*avx_mov_internal" - [(set (match_operand:AVXMODE16 0 "nonimmediate_operand" "=x,x ,m") - (match_operand:AVXMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] - "TARGET_AVX +(define_insn "*mov_internal" + [(set (match_operand:V16 0 "nonimmediate_operand" "=x,x ,m") + (match_operand:V16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] + "TARGET_SSE && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" { @@ -218,85 +236,51 @@ { case MODE_V8SF: case MODE_V4SF: - if (misaligned_operand (operands[0], mode) - || misaligned_operand (operands[1], mode)) + if (TARGET_AVX + && (misaligned_operand (operands[0], mode) + || misaligned_operand (operands[1], mode))) return "vmovups\t{%1, %0|%0, %1}"; else - return "vmovaps\t{%1, %0|%0, %1}"; + return "%vmovaps\t{%1, %0|%0, %1}"; + case MODE_V4DF: case MODE_V2DF: - if (misaligned_operand (operands[0], mode) - || misaligned_operand (operands[1], mode)) + if (TARGET_AVX + && (misaligned_operand (operands[0], mode) + || misaligned_operand (operands[1], mode))) return "vmovupd\t{%1, %0|%0, %1}"; else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) - return "vmovaps\t{%1, %0|%0, %1}"; + return "%vmovaps\t{%1, %0|%0, %1}"; else - return "vmovapd\t{%1, %0|%0, %1}"; - default: - if (misaligned_operand (operands[0], mode) - || misaligned_operand (operands[1], mode)) + return "%vmovapd\t{%1, %0|%0, %1}"; + + case MODE_OI: + case MODE_TI: + if (TARGET_AVX + && (misaligned_operand (operands[0], mode) + || misaligned_operand (operands[1], mode))) return "vmovdqu\t{%1, %0|%0, %1}"; else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) - return "vmovaps\t{%1, %0|%0, %1}"; + return "%vmovaps\t{%1, %0|%0, %1}"; else - return "vmovdqa\t{%1, %0|%0, %1}"; - } - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sselog1,ssemov,ssemov") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -;; All of these patterns are enabled for SSE1 as well as SSE2. -;; This is essential for maintaining stable calling conventions. - -(define_expand "mov" - [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "") - (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))] - "TARGET_SSE" -{ - ix86_expand_vector_move (mode, operands); - DONE; -}) + return "%vmovdqa\t{%1, %0|%0, %1}"; -(define_insn "*mov_internal" - [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "=x,x ,m") - (match_operand:SSEMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] - "TARGET_SSE - && (register_operand (operands[0], mode) - || register_operand (operands[1], mode))" -{ - switch (which_alternative) - { - case 0: - return standard_sse_constant_opcode (insn, operands[1]); - case 1: - case 2: - switch (get_attr_mode (insn)) - { - case MODE_V4SF: - return "movaps\t{%1, %0|%0, %1}"; - case MODE_V2DF: - if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) - return "movaps\t{%1, %0|%0, %1}"; - else - return "movapd\t{%1, %0|%0, %1}"; default: - if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) - return "movaps\t{%1, %0|%0, %1}"; - else - return "movdqa\t{%1, %0|%0, %1}"; + gcc_unreachable (); } default: gcc_unreachable (); } } [(set_attr "type" "sselog1,ssemov,ssemov") + (set_attr "prefix" "maybe_vex") (set (attr "mode") - (cond [(ior (ior (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0)) - (eq (symbol_ref "TARGET_SSE2") (const_int 0))) + (cond [(ne (symbol_ref "TARGET_AVX") (const_int 0)) + (const_string "") + (ior (ior + (ne (symbol_ref "optimize_function_for_size_p (cfun)") + (const_int 0)) + (eq (symbol_ref "TARGET_SSE2") (const_int 0))) (and (eq_attr "alternative" "2") (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES") (const_int 0)))) @@ -308,6 +292,19 @@ ] (const_string "TI")))]) +(define_insn "sse2_movq128" + [(set (match_operand:V2DI 0 "register_operand" "=x") + (vec_concat:V2DI + (vec_select:DI + (match_operand:V2DI 1 "nonimmediate_operand" "xm") + (parallel [(const_int 0)])) + (const_int 0)))] + "TARGET_SSE2" + "%vmovq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + ;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm. ;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded ;; from memory, we'd prefer to load the memory directly into the %xmm @@ -370,15 +367,7 @@ }) (define_expand "push1" - [(match_operand:AVX256MODE 0 "register_operand" "")] - "TARGET_AVX" -{ - ix86_expand_push (mode, operands[0]); - DONE; -}) - -(define_expand "push1" - [(match_operand:SSEMODE16 0 "register_operand" "")] + [(match_operand:V16 0 "register_operand" "")] "TARGET_SSE" { ix86_expand_push (mode, operands[0]); @@ -386,169 +375,84 @@ }) (define_expand "movmisalign" - [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "") - (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))] - "TARGET_AVX" -{ - ix86_expand_vector_move_misalign (mode, operands); - DONE; -}) - -(define_expand "movmisalign" - [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "") - (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))] + [(set (match_operand:V16 0 "nonimmediate_operand" "") + (match_operand:V16 1 "nonimmediate_operand" ""))] "TARGET_SSE" { ix86_expand_vector_move_misalign (mode, operands); DONE; }) -(define_expand "avx_movu" - [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "") - (unspec:AVXMODEF2P - [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")] +(define_expand "_movu" + [(set (match_operand:VF 0 "nonimmediate_operand" "") + (unspec:VF + [(match_operand:VF 1 "nonimmediate_operand" "")] UNSPEC_MOVU))] - "AVX_VEC_FLOAT_MODE_P (mode)" + "" { if (MEM_P (operands[0]) && MEM_P (operands[1])) operands[1] = force_reg (mode, operands[1]); }) -(define_insn "*avx_movu" - [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m") - (unspec:AVXMODEF2P - [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")] +(define_insn "*_movu" + [(set (match_operand:VF 0 "nonimmediate_operand" "=x,m") + (unspec:VF + [(match_operand:VF 1 "nonimmediate_operand" "xm,x")] UNSPEC_MOVU))] - "AVX_VEC_FLOAT_MODE_P (mode) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "vmovu\t{%1, %0|%0, %1}" + "!(MEM_P (operands[0]) && MEM_P (operands[1]))" + "%vmovu\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -(define_insn "sse2_movq128" - [(set (match_operand:V2DI 0 "register_operand" "=x") - (vec_concat:V2DI - (vec_select:DI - (match_operand:V2DI 1 "nonimmediate_operand" "xm") - (parallel [(const_int 0)])) - (const_int 0)))] - "TARGET_SSE2" - "%vmovq\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") (set_attr "prefix" "maybe_vex") - (set_attr "mode" "TI")]) - -(define_expand "_movu" - [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "SSE_VEC_FLOAT_MODE_P (mode)" -{ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (mode, operands[1]); -}) - -(define_insn "*_movu" - [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")] - UNSPEC_MOVU))] - "SSE_VEC_FLOAT_MODE_P (mode) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "movu\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "movu" "1") (set_attr "mode" "")]) -(define_expand "avx_movdqu" - [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "") - (unspec:AVXMODEQI - [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "TARGET_AVX" +(define_expand "_movdqu" + [(set (match_operand:VI1 0 "nonimmediate_operand" "") + (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "")] + UNSPEC_MOVU))] + "TARGET_SSE2" { if (MEM_P (operands[0]) && MEM_P (operands[1])) operands[1] = force_reg (mode, operands[1]); }) -(define_insn "*avx_movdqu" - [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m") - (unspec:AVXMODEQI - [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")] - UNSPEC_MOVU))] - "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "vmovdqu\t{%1, %0|%0, %1}" +(define_insn "*_movdqu" + [(set (match_operand:VI1 0 "nonimmediate_operand" "=x,m") + (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "xm,x")] + UNSPEC_MOVU))] + "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "%vmovdqu\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") - (set_attr "prefix" "vex") + (set (attr "prefix_data16") + (if_then_else + (ne (symbol_ref "TARGET_AVX") (const_int 0)) + (const_string "*") + (const_string "1"))) + (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_expand "sse2_movdqu" - [(set (match_operand:V16QI 0 "nonimmediate_operand" "") - (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "TARGET_SSE2" -{ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (V16QImode, operands[1]); -}) - -(define_insn "*sse2_movdqu" - [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m") - (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")] - UNSPEC_MOVU))] - "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "movdqu\t{%1, %0|%0, %1}" +(define_insn "_lddqu" + [(set (match_operand:VI1 0 "register_operand" "=x") + (unspec:VI1 [(match_operand:VI1 1 "memory_operand" "m")] + UNSPEC_LDDQU))] + "TARGET_SSE3" + "%vlddqu\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_insn "avx_movnt" - [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m") - (unspec:AVXMODEF2P - [(match_operand:AVXMODEF2P 1 "register_operand" "x")] - UNSPEC_MOVNT))] - "AVX_VEC_FLOAT_MODE_P (mode)" - "vmovnt\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -(define_insn "_movnt" - [(set (match_operand:SSEMODEF2P 0 "memory_operand" "=m") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "register_operand" "x")] - UNSPEC_MOVNT))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "movnt\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "mode" "")]) - -(define_insn "avx_movnt" - [(set (match_operand:AVXMODEDI 0 "memory_operand" "=m") - (unspec:AVXMODEDI - [(match_operand:AVXMODEDI 1 "register_operand" "x")] - UNSPEC_MOVNT))] - "TARGET_AVX" - "vmovntdq\t{%1, %0|%0, %1}" - [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set (attr "prefix_data16") + (if_then_else + (ne (symbol_ref "TARGET_AVX") (const_int 0)) + (const_string "*") + (const_string "0"))) + (set (attr "prefix_rep") + (if_then_else + (ne (symbol_ref "TARGET_AVX") (const_int 0)) + (const_string "*") + (const_string "1"))) + (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "sse2_movntv2di" - [(set (match_operand:V2DI 0 "memory_operand" "=m") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")] - UNSPEC_MOVNT))] - "TARGET_SSE2" - "movntdq\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - (define_insn "sse2_movntsi" [(set (match_operand:SI 0 "memory_operand" "=m") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] @@ -559,30 +463,31 @@ (set_attr "prefix_data16" "0") (set_attr "mode" "V2DF")]) -(define_insn "avx_lddqu" - [(set (match_operand:AVXMODEQI 0 "register_operand" "=x") - (unspec:AVXMODEQI - [(match_operand:AVXMODEQI 1 "memory_operand" "m")] - UNSPEC_LDDQU))] - "TARGET_AVX" - "vlddqu\t{%1, %0|%0, %1}" +(define_insn "_movnt" + [(set (match_operand:VF 0 "memory_operand" "=m") + (unspec:VF [(match_operand:VF 1 "register_operand" "x")] + UNSPEC_MOVNT))] + "TARGET_SSE" + "%vmovnt\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "")]) + +(define_insn "_movnt" + [(set (match_operand:VI8 0 "memory_operand" "=m") + (unspec:VI8 [(match_operand:VI8 1 "register_operand" "x")] + UNSPEC_MOVNT))] + "TARGET_SSE2" + "%vmovntdq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") - (set_attr "movu" "1") - (set_attr "prefix" "vex") + (set (attr "prefix_data16") + (if_then_else + (ne (symbol_ref "TARGET_AVX") (const_int 0)) + (const_string "*") + (const_string "1"))) + (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "sse3_lddqu" - [(set (match_operand:V16QI 0 "register_operand" "=x") - (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")] - UNSPEC_LDDQU))] - "TARGET_SSE3" - "lddqu\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") - (set_attr "movu" "1") - (set_attr "prefix_data16" "0") - (set_attr "prefix_rep" "1") - (set_attr "mode" "TI")]) - ; Expand patterns for non-temporal stores. At the moment, only those ; that directly map to insns are defined; it would be possible to ; define patterns for other modes that would expand to several insns. Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 172498) +++ config/i386/i386.c (working copy) @@ -15769,12 +15769,12 @@ ix86_expand_vector_move_misalign (enum m { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_avx_movups (op0, op1)); + emit_insn (gen_sse_movups (op0, op1)); return; } op0 = gen_lowpart (V16QImode, op0); op1 = gen_lowpart (V16QImode, op1); - emit_insn (gen_avx_movdqu (op0, op1)); + emit_insn (gen_sse2_movdqu (op0, op1)); break; case 32: op0 = gen_lowpart (V32QImode, op0); @@ -15792,7 +15792,7 @@ ix86_expand_vector_move_misalign (enum m switch (mode) { case V4SFmode: - emit_insn (gen_avx_movups (op0, op1)); + emit_insn (gen_sse_movups (op0, op1)); break; case V8SFmode: ix86_avx256_split_vector_move_misalign (op0, op1); @@ -15802,10 +15802,10 @@ ix86_expand_vector_move_misalign (enum m { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_avx_movups (op0, op1)); + emit_insn (gen_sse_movups (op0, op1)); return; } - emit_insn (gen_avx_movupd (op0, op1)); + emit_insn (gen_sse2_movupd (op0, op1)); break; case V4DFmode: ix86_avx256_split_vector_move_misalign (op0, op1); Index: testsuite/gcc.target/i386/avx256-unaligned-load-1.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-load-1.c (revision 172498) +++ testsuite/gcc.target/i386/avx256-unaligned-load-1.c (working copy) @@ -15,5 +15,5 @@ avx_test (void) } /* { dg-final { scan-assembler-not "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler "\\*sse_movups/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-load-3.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-load-3.c (revision 172498) +++ testsuite/gcc.target/i386/avx256-unaligned-load-3.c (working copy) @@ -15,5 +15,5 @@ avx_test (void) } /* { dg-final { scan-assembler-not "\\*avx_movupd256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movupd/1" } } */ +/* { dg-final { scan-assembler "\\*sse2_movupd/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-1.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-1.c (revision 172498) +++ testsuite/gcc.target/i386/avx256-unaligned-store-1.c (working copy) @@ -18,5 +18,5 @@ avx_test (void) } /* { dg-final { scan-assembler-not "\\*avx_movups256/2" } } */ -/* { dg-final { scan-assembler "movups.*\\*avx_movv4sf_internal/3" } } */ +/* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-3.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-3.c (revision 172498) +++ testsuite/gcc.target/i386/avx256-unaligned-store-3.c (working copy) @@ -18,5 +18,5 @@ avx_test (void) } /* { dg-final { scan-assembler-not "\\*avx_movupd256/2" } } */ -/* { dg-final { scan-assembler "movupd.*\\*avx_movv2df_internal/3" } } */ +/* { dg-final { scan-assembler "vmovupd.*\\*movv2df_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-load-2.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-load-2.c (revision 172498) +++ testsuite/gcc.target/i386/avx256-unaligned-load-2.c (working copy) @@ -25,5 +25,5 @@ avx_test (void) } /* { dg-final { scan-assembler-not "\\*avx_movdqu256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movdqu/1" } } */ +/* { dg-final { scan-assembler "\\*sse2_movdqu/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-2.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-2.c (revision 172498) +++ testsuite/gcc.target/i386/avx256-unaligned-store-2.c (working copy) @@ -25,5 +25,5 @@ avx_test (void) } /* { dg-final { scan-assembler-not "\\*avx_movdqu256/2" } } */ -/* { dg-final { scan-assembler "movdqu.*\\*avx_movv16qi_internal/3" } } */ +/* { dg-final { scan-assembler "vmovdqu.*\\*movv16qi_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */