From patchwork Thu May 19 19:32:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 96449 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id DF17EB718A for ; Fri, 20 May 2011 05:33:20 +1000 (EST) Received: (qmail 31342 invoked by alias); 19 May 2011 19:33:17 -0000 Received: (qmail 31319 invoked by uid 22791); 19 May 2011 19:33:16 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST, TW_ZJ, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-pz0-f47.google.com (HELO mail-pz0-f47.google.com) (209.85.210.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 19 May 2011 19:32:54 +0000 Received: by pzk36 with SMTP id 36so1461637pzk.20 for ; Thu, 19 May 2011 12:32:53 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.125.11 with SMTP id x11mr318372wfc.153.1305833573571; Thu, 19 May 2011 12:32:53 -0700 (PDT) Received: by 10.142.108.7 with HTTP; Thu, 19 May 2011 12:32:53 -0700 (PDT) Date: Thu, 19 May 2011 21:32:53 +0200 Message-ID: Subject: [PATCH, i386]: Fix __builtin_ia32_rdrand*_step expansion From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! Attached patch fixes ICE with -m32 -march=i386 -mrdrand on freebsd [1]. The problem was that __builtin_ia32_rdrand*_step expands to a sequence that includes conditional move, so we should set TARGET_CMOVE. Additionally, the patch fixes expansion with void return: void foo (unsigned short *x) { _rdrand16_step (x); } And finally, move to the memory was moved closer to the producer, to eventually generate few live registers. 2011-05-19 Uros Bizjak * config/i386/i386.c (option_override_internal): Enable TARGET_CMOVE when TARGET_RDRND is active. (ix86_expand_builtin) : Generate dummy SImode target register when target is NULL. Patch was bootstrapped and tested on x86_64-pc-linux-gnu, will be committed to SVN mainline and 4.6. [1] http://gcc.gnu.org/ml/gcc-testresults/2011-05/msg01884.html Index: i386.c =================================================================== --- i386.c (revision 173914) +++ i386.c (working copy) @@ -4091,8 +4091,9 @@ ix86_option_override_internal (bool main } /* For sane SSE instruction set generation we need fcomi instruction. - It is safe to enable all CMOVE instructions. */ - if (TARGET_SSE) + It is safe to enable all CMOVE instructions. Also, intrinsic expands + to a sequence that includes conditional move. */ + if (TARGET_SSE || TARGET_RDRND) TARGET_CMOVE = 1; /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */ @@ -27613,6 +27614,12 @@ rdrand_step: op0 = gen_reg_rtx (mode0); emit_insn (GEN_FCN (icode) (op0)); + arg0 = CALL_EXPR_ARG (exp, 0); + op1 = expand_normal (arg0); + if (!address_operand (op1, VOIDmode)) + op1 = copy_addr_to_reg (op1); + emit_move_insn (gen_rtx_MEM (mode0, op1), op0); + op1 = gen_reg_rtx (SImode); emit_move_insn (op1, CONST1_RTX (SImode)); @@ -27627,17 +27634,13 @@ rdrand_step: else op2 = gen_rtx_SUBREG (SImode, op0, 0); + if (target == 0) + target = gen_reg_rtx (SImode); + pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), const0_rtx); - emit_insn (gen_rtx_SET (VOIDmode, op1, + emit_insn (gen_rtx_SET (VOIDmode, target, gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1))); - emit_move_insn (target, op1); - - arg0 = CALL_EXPR_ARG (exp, 0); - op1 = expand_normal (arg0); - if (!address_operand (op1, VOIDmode)) - op1 = copy_addr_to_reg (op1); - emit_move_insn (gen_rtx_MEM (mode0, op1), op0); return target; default: