From patchwork Wed May 25 19:24:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 97403 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 9B6A6B6F90 for ; Thu, 26 May 2011 05:24:27 +1000 (EST) Received: (qmail 12712 invoked by alias); 25 May 2011 19:24:25 -0000 Received: (qmail 12702 invoked by uid 22791); 25 May 2011 19:24:24 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST, TW_OV, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-qy0-f175.google.com (HELO mail-qy0-f175.google.com) (209.85.216.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 25 May 2011 19:24:09 +0000 Received: by qyk35 with SMTP id 35so2314868qyk.20 for ; Wed, 25 May 2011 12:24:08 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.106.32 with SMTP id v32mr4130616qco.77.1306351448393; Wed, 25 May 2011 12:24:08 -0700 (PDT) Received: by 10.229.11.143 with HTTP; Wed, 25 May 2011 12:24:08 -0700 (PDT) In-Reply-To: References: <20110524155424.GA7400@intel.com> Date: Wed, 25 May 2011 12:24:08 -0700 Message-ID: Subject: Re: PATCH: PR target/49142: Invalid 8bit register operand From: "H.J. Lu" To: Uros Bizjak Cc: gcc-patches@gcc.gnu.org X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Wed, May 25, 2011 at 12:11 PM, Uros Bizjak wrote: > On Wed, May 25, 2011 at 6:20 PM, H.J. Lu wrote: > >>>>>> We are working on a new optimization, which turns off TARGET_MOVX. >>>>>> GCC generates: >>>>>> >>>>>> movb %ah, %dil >>>>>> >>>>>> But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand >>>>>> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk >>>>>> if there is no regression? and Replace >>>       q_regs_operand with QIreg_operand. >>>       ( >>>>> >>>>> If this is the case, then please change "q_regs_operand" predicate to >>>>> accept just QI_REG_P registers. >>>>> >>>> >>>> I thought about it.  It is a problem only with %[abcd]h.  I am not sure if >>>> changing q_regs_operand to  accept just QI_REG_P registers will negatively >>>> impact >>> >>> I see. The patch is OK then, but for consistency, please change the >>> predicate of *movqi_extv_1*movqi_extzv_2 as well. Oh, and the >>> "register_operand" check in "type" calculation can be removed. >>> >>> Thanks, >>> Uros. >>> >> >> This is what I checked in. >> >> Thanks. >> >> -- >> H.J. >> --- >> 2011-05-25  H.J. Lu   >> >>        PR target/49142 >>        * config/i386/i386.md (*movqi_extv_1_rex64): Remove >>        "register_operand" check and replace q_regs_operand with >>        QIreg_operand in "type" calculation. >>        (*movqi_extv_1): Likewise. >>        (*movqi_extzv_2_rex64): Likewise. >>        (*movqi_extzv_2): Likewise. > > Er, I didn't mean to remove register_operand check from 32bit > patterns... there, operand 0 can also be memory operand due to > "nonimmediate_operand" constraint. Ooops. I am checking in this. Thanks. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ed1834f..1afef8e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2011-05-25 H.J. Lu + * config/i386/i386.md (*movqi_extv_1)): Put back + "register_operand" check in "type" calculation. + (*movqi_extzv_2): Likewise. + +2011-05-25 H.J. Lu + * doc/extend.texi (X86 Built-in Functions): Update pause intrinsic. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1cdbe7e..13a1cde 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2514,9 +2514,10 @@ } } [(set (attr "type") - (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" "")) - (ne (symbol_ref "TARGET_MOVX") - (const_int 0))) + (if_then_else (and (match_operand:QI 0 "register_operand" "") + (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (ne (symbol_ref "TARGET_MOVX") + (const_int 0)))) (const_string "imovx") (const_string "imov"))) (set (attr "mode") @@ -2578,9 +2579,10 @@ } } [(set (attr "type") - (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" "")) - (ne (symbol_ref "TARGET_MOVX") - (const_int 0))) + (if_then_else (and (match_operand:QI 0 "register_operand" "") + (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (ne (symbol_ref "TARGET_MOVX") + (const_int 0)))) (const_string "imovx") (const_string "imov"))) (set (attr "mode")