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[MIPS] Correct latency of loads in M5100

Message ID B5E67142681B53468FAF6B7C313565624F4EBEC2@hhmail02.hh.imgtec.org
State New
Headers show

Commit Message

Robert Suchanek May 13, 2016, 2:49 p.m. UTC 
Hi,

A small patch to correct the latency for M5100.

Ok to commit?

Regards,
Robert

2016-05-13  Matthew Fortune  <matthew.fortune@imgtec.com>

	* config/mips/m5100.md (m51_int_load): Update the latency to 2.

---
 gcc/config/mips/m5100.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Matthew Fortune May 16, 2016, 9:33 a.m. UTC | #1 
Robert Suchanek <Robert.Suchanek@imgtec.com> writes:
> A small patch to correct the latency for M5100.
> 
> Ok to commit?

> 	* config/mips/m5100.md (m51_int_load): Update the latency to 2.

OK.

Matthew
Robert Suchanek May 16, 2016, 2:25 p.m. UTC | #2 
> > Ok to commit?
> 
> > 	* config/mips/m5100.md (m51_int_load): Update the latency to 2.
> 
> OK.

Committed - r236288

Robert
diff mbox

Patch

diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md
index f69fc7f..8d87b70 100644
--- a/gcc/config/mips/m5100.md
+++ b/gcc/config/mips/m5100.md
@@ -65,7 +65,7 @@  (define_insn_reservation "m51_int_jump" 1
 
 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
 ;; prefetch: prefetch, prefetchx
-(define_insn_reservation "m51_int_load" 3
+(define_insn_reservation "m51_int_load" 2
   (and (eq_attr "cpu" "m5100")
        (eq_attr "type" "load,prefetch,prefetchx"))
   "m51_alu")