From patchwork Wed Jul 8 10:41:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Suchanek X-Patchwork-Id: 492846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0B3E6140788 for ; Wed, 8 Jul 2015 20:41:46 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=vvKKaa2e; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=xtd 0EkbiaZpZtdSBu5JjfIUwxFHtzx7mPekARZqe6Ego5yaudaveI9luSgYb8WeL3uS dZFm7HZw52h/MtsTcD+N1oqHrO/feihhIaa362eo4Aqkxlv7Tk5JvJmluvX88E+s 2M82z7SRiCZR5NzD/+snyNDLHoIkwrVCNGDbTirw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=RozCWHSt7 a8tc5pTatS5Y4osmoo=; b=vvKKaa2e4cq9QH2uI+0Yh8nyIVqgxf8Sbn+CIgEFy rNmmh05F6E6BhWhfYBc+Eoy3CirMCxniL953PMr/aUIAnPzKIADbnwa3hUZ0mST8 BOWIo3Bn65aljwERe5v+G3YBNmf5aGG96TbwfrQipez/7nRUrKJakQUntLhwMz1p dg= Received: (qmail 57450 invoked by alias); 8 Jul 2015 10:41:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 57434 invoked by uid 89); 8 Jul 2015 10:41:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 08 Jul 2015 10:41:38 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id EE12C4F0F4388; Wed, 8 Jul 2015 11:41:33 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 8 Jul 2015 11:41:35 +0100 Received: from hhmail02.hh.imgtec.org ([::1]) by hhmail02.hh.imgtec.org ([::1]) with mapi id 14.03.0235.001; Wed, 8 Jul 2015 11:41:35 +0100 From: Robert Suchanek To: Matthew Fortune , "Catherine_Moore@mentor.com" , "gcc-patches@gcc.gnu.org" Subject: [PATCH, MIPS] Support interrupt handlers with hard-float Date: Wed, 8 Jul 2015 10:41:34 +0000 Message-ID: MIME-Version: 1.0 X-IsSubscribed: yes Hi Matthew/Catherine, The attached patch removes the restriction to compile a TU with an ISR with -mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled in an ISR for -mhard-float. Ok to apply? Regards, Robert gcc/ * config/mips/mips.c (mips_compute_frame_info): Allow -mhard-float in interrupt attribute. (mips_expand_prologue): Disable the floating point unit in an ISR for -mhard-float. * config/mips/mips.h (SR_COP1): New define. --- gcc/config/mips/mips.c | 10 ++++++++-- gcc/config/mips/mips.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b6ad7db..18cb2bc 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -10424,8 +10424,6 @@ mips_compute_frame_info (void) { if (mips_isa_rev < 2) error ("the % attribute requires a MIPS32r2 processor or greater"); - else if (TARGET_HARD_FLOAT) - error ("the % attribute requires %<-msoft-float%>"); else if (TARGET_MIPS16) error ("interrupt handlers cannot be MIPS16 functions"); else @@ -11676,6 +11674,14 @@ mips_expand_prologue (void) GEN_INT (5), GEN_INT (SR_IE), gen_rtx_REG (SImode, GP_REG_FIRST))); + + if (TARGET_HARD_FLOAT) + /* Disable COP1 for hard-float. This will lead to an exception + if floating-point code is executed in an ISR. */ + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), + GEN_INT (1), + GEN_INT (SR_COP1), + gen_rtx_REG (SImode, GP_REG_FIRST))); } else { diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0e14f90..24cf65c 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1807,6 +1807,8 @@ FP_ASM_SPEC "\ /* Request Interrupt Priority Level is from bit 10 to bit 15 of the cause register for the EIC interrupt mode. */ #define CAUSE_IPL 10 +/* COP1 Enable is at bit 29 of the status register. */ +#define SR_COP1 29 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ #define SR_IPL 10 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status