Message ID | B5E67142681B53468FAF6B7C31356562441AA1E0@hhmail02.hh.imgtec.org |
---|---|
State | New |
Headers | show |
> -----Original Message----- > From: Robert Suchanek [mailto:Robert.Suchanek@imgtec.com] > Sent: Wednesday, July 08, 2015 6:42 AM > To: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org > Subject: [PATCH, MIPS] Support interrupt handlers with hard-float > > Hi Matthew/Catherine, > > The attached patch removes the restriction to compile a TU with an ISR with - > mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled in > an ISR for -mhard-float. > > Ok to apply? Yes, this one is OK. > > gcc/ > * config/mips/mips.c (mips_compute_frame_info): Allow -mhard- > float in > interrupt attribute. > (mips_expand_prologue): Disable the floating point unit in an ISR for > -mhard-float. > * config/mips/mips.h (SR_COP1): New define.
Hi, > > Hi Matthew/Catherine, > > > > The attached patch removes the restriction to compile a TU with an ISR with > - > > mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled > in > > an ISR for -mhard-float. > > > > Ok to apply? > > Yes, this one is OK. Committed as r225818. Regards, Robert
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b6ad7db..18cb2bc 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -10424,8 +10424,6 @@ mips_compute_frame_info (void) { if (mips_isa_rev < 2) error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater"); - else if (TARGET_HARD_FLOAT) - error ("the %<interrupt%> attribute requires %<-msoft-float%>"); else if (TARGET_MIPS16) error ("interrupt handlers cannot be MIPS16 functions"); else @@ -11676,6 +11674,14 @@ mips_expand_prologue (void) GEN_INT (5), GEN_INT (SR_IE), gen_rtx_REG (SImode, GP_REG_FIRST))); + + if (TARGET_HARD_FLOAT) + /* Disable COP1 for hard-float. This will lead to an exception + if floating-point code is executed in an ISR. */ + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), + GEN_INT (1), + GEN_INT (SR_COP1), + gen_rtx_REG (SImode, GP_REG_FIRST))); } else { diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0e14f90..24cf65c 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1807,6 +1807,8 @@ FP_ASM_SPEC "\ /* Request Interrupt Priority Level is from bit 10 to bit 15 of the cause register for the EIC interrupt mode. */ #define CAUSE_IPL 10 +/* COP1 Enable is at bit 29 of the status register. */ +#define SR_COP1 29 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ #define SR_IPL 10 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status