From patchwork Wed Apr 26 12:39:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 755460 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wCfn203Htz9s8c for ; Wed, 26 Apr 2017 22:40:17 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="y0MHDdHQ"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=dzj D8t/rmpiSG37lMaxQ0dVg6dRAFZT9bUsiic1JGq4A4l5k87tbncFm9nTwpI/EuIv ycZfG7O4sRi2+G6XbUysSg1q8BKIExOITIGq73h6qOaL14iBss0PpdF23yTcxyM4 c5xkXnoi8OquTYXBZc+6+9Bm6Cy1nfanXI9aRj8s= DKIM-Signature: v=1; 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Wed, 26 Apr 2017 12:40:00 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM5PR0802MB2385.eurprd08.prod.outlook.com (10.175.43.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1047.13; Wed, 26 Apr 2017 12:39:58 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.1061.013; Wed, 26 Apr 2017 12:39:52 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd , James Greenhalgh , "Richard Earnshaw" Subject: [PATCH][AArch64] Improve float to int moves Date: Wed, 26 Apr 2017 12:39:51 +0000 Message-ID: authentication-results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=arm.com; x-microsoft-exchange-diagnostics: 1; AM5PR0802MB2385; 7:yEpQa9GLcQOhQMn1485GBCElwbSST/ZJMN4yjFyWaow313WzLO3GFKrJtPMWmcH5pKJDQo0c058fdeJGQYovNabeNzBLfXAsVZJ84Xp7ApIztYfk4tJNE5ebQO2dyirzNsKPWHwKEtzptHHUG85QAUDoC8rXiaNxxPcOEeqeZKBv5BKHl2FffQ1Bt4lL13HAnleelRkZ9thC+jmh59H9QSNyL00+SP7HHfVOIKajMfFZjq93JPtmrr5cp7XhmqdL/x8fgpTmJOp9d0JS3eLZc6UEX+Vrr4kXjLy1MpG24LZf6BjAsLu+EMNc/GJAlCcr29Y2sm4Akb1uYwwfpADKmA== x-ms-office365-filtering-correlation-id: f0576da3-9a6e-43f4-5f22-08d48ca155b2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM5PR0802MB2385; H:AM5PR0802MB2610.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Apr 2017 12:39:51.9807 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2385 Float to int moves currently generate inefficient code due to hacks used in the movsi and movdi patterns. The 'r = w' variant uses '*' which explicitly tells the register allocator to ignore it. As a result float to int moves typically spill to the stack, which is extremely inefficient. For example: static inline unsigned asuint (float f) { union { float f; unsigned i; } u = {f}; return u.i; } float foo (float x) { unsigned i = asuint (x); if (__builtin_expect (i > 42, 0)) return x*x; return i; } generates: sub sp, sp, #16 str s0, [sp, 12] ldr w0, [sp, 12] cmp w0, 42 bhi .L7 scvtf s0, w0 add sp, sp, 16 ret .L7: fmul s0, s0, s0 add sp, sp, 16 ret Removing '*' from the variant generates: fmov w0, s0 cmp w0, 42 bhi .L6 scvtf s0, w0 ret .L6: fmul s0, s0, s0 ret Passes regress & bootstrap, OK for commit? ChangeLog: 2017-04-26 Wilco Dijkstra * config/aarch64/aarch64.md (movsi_aarch64): Remove '*' from r=w. (movdi_aarch64): Likewise. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 51368e29f2d1fd12f48a972bd81a08589a720e07..d656e92e1ff02bdc90c824227ec3b2e1ccfe665a 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1026,8 +1026,8 @@ (define_expand "mov" ) (define_insn_and_split "*movsi_aarch64" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r ,*w, r,*w") - (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,m, m,rZ,*w,S,Ush,rZ,*w,*w"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r ,*w,r,*w") + (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,m, m,rZ,*w,S,Ush,rZ,w,*w"))] "(register_operand (operands[0], SImode) || aarch64_reg_or_zero (operands[1], SImode))" "@ @@ -1058,8 +1058,8 @@ (define_insn_and_split "*movsi_aarch64" ) (define_insn_and_split "*movdi_aarch64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r, *w, r,*w,w") - (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,n,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r, *w,r,*w,w") + (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,n,m, m,rZ,*w,S,Ush,rZ,w,*w,Dd"))] "(register_operand (operands[0], DImode) || aarch64_reg_or_zero (operands[1], DImode))" "@