From patchwork Thu Nov 10 17:11:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 693371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tF8jm2rh8z9vDZ for ; Fri, 11 Nov 2016 04:12:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Hj1541Cb"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=Y/v mTBTHrIvRtCZrj707JugXTHu3QtdPOWo2fVFqM3heyEqsDM96cLol1HG8CH7eCm3 rFo5OXcizRgY7i4lhpr8DBbS9fSITr7F58mXVYg+HP1SgsHUyR0YxYFWhTWAlvjW Kub8kgGxJ4xL15Hz/bJlemrZkZq+9WEyVL4ItQBY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=oPBZsHEeG 3bSdElmhXLLeR6gDBI=; b=Hj1541CbH2mS9yA+Fv1jDI7y1rI8Azq4sCWCnHl2g f3iO/0q5rbTSCYY2AZyFk+8CwasLJVq5Jnxh2eFT7TxgyBDo47KDqYQbAy7sX80z ObraY7jQQHq7mlFoN8z7orbGGVsdeFrZYZd5q9Ldya63sZDook55yoBGeL0I4Wwi EI= Received: (qmail 66041 invoked by alias); 10 Nov 2016 17:11:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65998 invoked by uid 89); 10 Nov 2016 17:11:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=no version=3.3.2 spammy=set_attr, Integer, XXX, xxx X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0084.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.84) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Nov 2016 17:11:43 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.721.10; Thu, 10 Nov 2016 17:11:39 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.0721.010; Thu, 10 Nov 2016 17:11:39 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd Subject: [PATCH 1/2][AArch64] Add bfx attribute Date: Thu, 10 Nov 2016 17:11:39 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-microsoft-exchange-diagnostics: 1; AM5PR0802MB2610; 7:53ngj8khXc/No88jcfjjCqzYES8qllm026+G5YpZLqJO72DvVYysSH+bK072Bex7YykMu2ZbgxhWFgdLzyutMgB5HiAp6XFNzOuE9ZCS1RImJZX8jPmmQ2aLtl0/g+qi+0I5FIido/HKPtOq9jtwqIkpkR4P7CkZ61canG/6CWl0LQnln9L1nSm6m45WCytG4yim04KkhBkosAKvvg5GuriV3/k4Gg3lYM36JblhGokZ/GJAwn2mqCo0XlDPw5o9Hwz430goI6DkvgU565wX3xv4M11UUBwRTre51G/F8JVChckgPxMf2bHA59NaOI1ByKAvjBdv+7eb6b1pFJj+vV42xc6EzIPhwLSwI4Bzlvg= x-ms-office365-filtering-correlation-id: 356b3e9e-2437-48c7-136f-08d4098ca2e3 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:AM5PR0802MB2610; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026); SRVR:AM5PR0802MB2610; BCL:0; PCL:0; RULEID:; SRVR:AM5PR0802MB2610; x-forefront-prvs: 01221E3973 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(7916002)(377424004)(199003)(189002)(54534003)(87936001)(66066001)(81166006)(81156014)(8936002)(189998001)(7846002)(54356999)(8676002)(4001150100001)(86362001)(68736007)(586003)(575784001)(2906002)(4326007)(9686002)(97736004)(122556002)(3846002)(6116002)(102836003)(7736002)(76576001)(5660300001)(50986999)(305945005)(33656002)(92566002)(6916009)(2900100001)(101416001)(450100001)(3280700002)(3660700001)(7696004)(74316002)(77096005)(106116001)(110136003)(105586002)(106356001)(21314002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM5PR0802MB2610; H:AM5PR0802MB2610.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Nov 2016 17:11:39.7863 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2610 Currently the SBFM, UBFM and BFM instructions all use the attribute "bfm". SBFM and UBFM include all shifts on AArch64, which are simpler than bitfield insert. Add a new bfx attribute for these instructions so that they can be modelled more accurately in the future. There is no difference in code generation. ChangeLog: 2016-11-10 Wilco Dijkstra * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3) Use bfx attribute. (aarch64_lshr_sisd_or_int_3): Likewise. (aarch64_ashr_sisd_or_int_3): Likewise. (si3_insn_uxtw): Likewise. (3_insn): Likewise. (_ashl): Likewise. (zero_extend_lshr): Likewise. (extend_ashr): Likewise. (): Likewise. (insv): Likewise. (andim_ashift_bfiz): Likewise. * config/aarch64/thunderx.md (thunderx_shift): Add bfx. * config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise. * config/arm/cortex-a57.md (cortex_a57_alu): Add bfx. * config/arm/exynos-m1.md (exynos_m1_alu): Add bfx. (exynos_m1_alu_p): Likewise. * config/arm/types.md: Add bfx. * config/arm/xgene1.md (xgene1_bfm): Add bfx. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 62eda569f9b642ac569a61718d7debf7eae1b59e..afd463602af4c3f19db8f8cc834aa8cf0b78867e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3955,7 +3955,7 @@ shl\t%0, %1, %2 ushl\t%0, %1, %2" [(set_attr "simd" "no,no,yes,yes") - (set_attr "type" "bfm,shift_reg,neon_shift_imm, neon_shift_reg")] + (set_attr "type" "bfx,shift_reg,neon_shift_imm, neon_shift_reg")] ) ;; Logical right shift using SISD or Integer instruction @@ -3972,7 +3972,7 @@ # #" [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfm,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] ) (define_split @@ -4019,7 +4019,7 @@ # #" [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfm,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] ) (define_split @@ -4129,7 +4129,7 @@ "@ \\t%w0, %w1, %2 \\t%w0, %w1, %w2" - [(set_attr "type" "bfm,shift_reg")] + [(set_attr "type" "bfx,shift_reg")] ) (define_insn "*3_insn" @@ -4141,7 +4141,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "\t%w0, %w1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "*extr5_insn" @@ -4234,7 +4234,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "bfiz\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "*zero_extend_lshr" @@ -4247,7 +4247,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "ubfx\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "*extend_ashr" @@ -4260,7 +4260,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "sbfx\\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) ;; ------------------------------------------------------------------- @@ -4283,7 +4283,7 @@ (match_operand 3 "const_int_operand" "n")))] "" "bfx\\t%0, %1, %3, %2" - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) ;; Bitfield Insert (insv) @@ -4365,7 +4365,7 @@ : GEN_INT ( - UINTVAL (operands[2])); return "bfiz\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below @@ -4377,7 +4377,7 @@ (match_operand 3 "const_int_operand" "n")))] "aarch64_mask_and_shift_for_ubfiz_p (mode, operands[3], operands[2])" "ubfiz\\t%0, %1, %2, %P3" - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "bswap2" diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index 058713a2ad98a364d36a3faaf0e93c39cb89adbc..7c1c28b0498cfe0129e3f0de7e29e31536fe421a 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -39,7 +39,7 @@ (define_insn_reservation "thunderx_shift" 1 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev")) + (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev")) "thunderx_pipe0 | thunderx_pipe1") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 70c0f4daabe0ccb8e32808f1af51f5460e087a18..eb6d0b04976aaf441dd95cc43d02918226e75387 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -93,7 +93,7 @@ (and (eq_attr "tune" "cortexa53") (eq_attr "type" "alu_shift_imm,alus_shift_imm, crc,logic_shift_imm,logics_shift_imm, - alu_ext,alus_ext,bfm,extend,mvn_shift")) + alu_ext,alus_ext,bfm,bfx,extend,mvn_shift")) "cortex_a53_slot_any") (define_insn_reservation "cortex_a53_alu_shift_reg" 3 diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index 85b18e5970f6cbb4f11e76d7f461a9a548fc7ce2..da461846baa5b28ce3d9c9f731dbfd7becb31a85 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -297,7 +297,7 @@ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\ + adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\ rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index 318b151d64697001d0082295e54486a2ffcaa6e5..00574d7930f23c36005648cddca285405ced8a8c 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -358,7 +358,7 @@ (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\ alu_sreg, alus_sreg, logic_reg, logics_reg,\ adc_imm, adcs_imm, adc_reg, adcs_reg,\ - adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\ + adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\ shift_imm, shift_reg, rotate_imm, extend,\ mov_imm, mov_reg,\ mvn_imm, mvn_reg,\ @@ -372,7 +372,7 @@ (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\ alu_sreg, alus_sreg, logic_reg, logics_reg,\ adc_imm, adcs_imm, adc_reg, adcs_reg,\ - adr, bfm, clz, rbit, rev, alu_dsp_reg,\ + adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\ shift_imm, shift_reg, rotate_imm, extend,\ mov_imm, mov_reg,\ mvn_imm, mvn_reg,\ diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 25f79b4d010ae24c14d97d9fead93db1eff42f32..7a95a3704d0907fcaf42463c5803cbff82b29fa1 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -51,6 +51,7 @@ ; alus_shift_imm as alu_shift_imm, setting condition flags. ; alus_shift_reg as alu_shift_reg, setting condition flags. ; bfm bitfield move operation. +; bfx bitfield extract operation. ; block blockage insn, this blocks all functional units. ; branch branch. ; call subroutine call. @@ -557,6 +558,7 @@ alus_shift_imm,\ alus_shift_reg,\ bfm,\ + bfx,\ block,\ branch,\ call,\ diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index b7aeac6916353f9a02b56821e3df3c2f43fc2946..4f27b28461f23aff6720cd1ba54c46fa9ae574ce 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -164,7 +164,7 @@ (define_insn_reservation "xgene1_bfm" 2 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "bfm")) + (eq_attr "type" "bfm,bfx")) "xgene1_decode1op,xgene1_fsu") (define_insn_reservation "xgene1_f_rint" 5