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Thu, 08 Dec 2016 15:31:03 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM5PR0801MB2084.eurprd08.prod.outlook.com (10.168.158.150) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.761.9; Thu, 8 Dec 2016 15:31:00 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.0771.008; Thu, 8 Dec 2016 15:31:00 +0000 From: Wilco Dijkstra To: GCC Patches , James Greenhalgh CC: nd Subject: [PATCH][AArch64] Fix PR78733 Date: Thu, 8 Dec 2016 15:30:59 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-office365-filtering-correlation-id: 92fadd3b-9142-4838-76e3-08d41f7f3675 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:AM5PR0801MB2084; x-microsoft-exchange-diagnostics: 1; AM5PR0801MB2084; 7:chxF7Y8yKpT+QToAJe6JHntP2l+e7HtLaP6GPRgGt8bMV0xa2glx2WGH6G7BLpkYC870Tg57xF2LtVsb4EoPDauoACHChlYGno9/s9GKHP1XBUIQ60+WOZLuE7cBjT6MyqOaoq2OtzF8+2snFRng63LkSQlJOq9R4k3HORQaihSsXs3QqyCgoJgsAjMxhqWoQR+CELCrgen36L3trAL/P+q7vioJURXqEdRIsMrKgKoiRBNK3wLmn27SB7AcOW366aHflaUhJ+8Ong4/gWTzJuPpk9ER0KYy79ravX4gGGBabGV2F5qxSbTOBUrXrjCC5neZdgLx07GDt9z3fv0v9nz0h/s8WWfXREgC9CctC9LptASrqk2vNSOJYstk2+12ombba8mgzM7WKRCBzeAQURMJ0UBcG9DhBx3TeNEZdzdeA0siNtoRKCCZ/jrXjKIxCgd5JGPz56s8BwValtsHrA== nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); 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SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Dec 2016 15:30:59.7424 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0801MB2084 This patch fixes an issue in aarch64_classify_address. TImode and TFmode can either use a 64-bit LDP/STP or 128-bit LDR/STR. The addressing mode must be carefully modelled as the intersection of both. This is done for the immediate offsets, however load_store_pair_p must be set as well to avoid LDP with a PC-relative address if aarch64_pcrelative_literal_loads is true. Bootstrap passes with aarch64_pcrelative_literal_loads=true. ChangeLog: 2015-12-08 Wilco Dijkstra PR target/78733 * config/aarch64/aarch64.c (aarch64_classify_address): Set load_store_pair_p for TImode and TFmode. /testsuite * gcc.target/aarch64/pr78733.c: New test. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 48efa37b89551264e25effab1dddbcb490fad085..a95f9c183fcd1db95a8366d1d5b5aa878ee51a6c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4230,8 +4230,11 @@ aarch64_classify_address (struct aarch64_address_info *info, enum rtx_code code = GET_CODE (x); rtx op0, op1; - /* On BE, we use load/store pair for all large int mode load/stores. */ + /* On BE, we use load/store pair for all large int mode load/stores. + TI/TFmode may also use a load/store pair. */ bool load_store_pair_p = (outer_code == PARALLEL + || mode == TImode + || mode == TFmode || (BYTES_BIG_ENDIAN && aarch64_vect_struct_mode_p (mode))); diff --git a/gcc/testsuite/gcc.target/aarch64/pr78733.c b/gcc/testsuite/gcc.target/aarch64/pr78733.c new file mode 100644 index 0000000000000000000000000000000000000000..ce462cedf9f049feb03addfb010b2f339972c337 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr78733.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpc-relative-literal-loads" } */ + +__int128 +t (void) +{ + return (__int128)1 << 80; +} + +/* { dg-final { scan-assembler "adr" } } */