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Thu, 23 Feb 2017 16:58:51 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM5PR0802MB2385.eurprd08.prod.outlook.com (10.175.43.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.933.12; Thu, 23 Feb 2017 16:58:48 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.0933.011; Thu, 23 Feb 2017 16:58:48 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd , Kyrill Tkachov , "Richard Earnshaw" Subject: Re: [PATCH][ARM] Remove DImode expansions for 1-bit shifts Date: Thu, 23 Feb 2017 16:58:48 +0000 Message-ID: References: , In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-office365-filtering-correlation-id: 9597f469-1e0a-4eb2-b493-08d45c0d3c7a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081); 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM5PR0802MB2385; H:AM5PR0802MB2610.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Feb 2017 16:58:48.4136 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2385 ping From: Wilco Dijkstra Sent: 17 January 2017 19:23 To: GCC Patches Cc: nd; Kyrill Tkachov; Richard Earnshaw Subject: [PATCH][ARM] Remove DImode expansions for 1-bit shifts     A left shift of 1 can always be done using an add, so slightly adjust rtx cost for DImode left shift by 1 so that adddi3 is preferred in all cases, and the arm_ashldi3_1bit is redundant. DImode right shifts of 1 are rarely used (6 in total in the GCC binary), so there is little benefit of the arm_ashrdi3_1bit and arm_lshrdi3_1bit patterns. Bootstrap OK on arm-linux-gnueabihf. ChangeLog: 2017-01-17  Wilco Dijkstra          * config/arm/arm.md (ashldi3): Remove shift by 1 expansion.         (arm_ashldi3_1bit): Remove pattern.         (ashrdi3): Remove shift by 1 expansion.         (arm_ashrdi3_1bit): Remove pattern.         (lshrdi3): Remove shift by 1 expansion.         (arm_lshrdi3_1bit): Remove pattern.         * config/arm/arm.c (arm_rtx_costs_internal): Slightly increase         cost of ashldi3 by 1.         * config/arm/neon.md (ashldi3_neon): Remove shift by 1 expansion.         (di3_neon): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7d82ba358306189535bf7eee08a54e2f84569307..d47f4005446ff3e81968d7888c6573c0360cfdbd 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9254,6 +9254,9 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,                     + rtx_cost (XEXP (x, 0), mode, code, 0, speed_p));            if (speed_p)              *cost += 2 * extra_cost->alu.shift; +         /* Slightly disparage left shift by 1 at so we prefer adddi3.  */ +         if (code == ASHIFT && XEXP (x, 1) == CONST1_RTX (SImode)) +           *cost += 1;            return true;          }        else if (mode == SImode) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 0d69c8be9a2f98971c23c3b6f1659049f369920e..92b734ca277079f5f7343c7cc21a343f48d234c5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4061,12 +4061,6 @@      {        rtx scratch1, scratch2;   -      if (operands[2] == CONST1_RTX (SImode)) -        { -          emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1])); -          DONE; -        } -        /* Ideally we should use iwmmxt here if we could know that operands[1]           ends up already living in an iwmmxt register. Otherwise it's           cheaper to have the alternate code being generated than moving @@ -4083,18 +4077,6 @@    "  )   -(define_insn "arm_ashldi3_1bit" -  [(set (match_operand:DI            0 "s_register_operand" "=r,&r") -        (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") -                   (const_int 1))) -   (clobber (reg:CC CC_REGNUM))] -  "TARGET_32BIT" -  "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" -  [(set_attr "conds" "clob") -   (set_attr "length" "8") -   (set_attr "type" "multiple")] -) -  (define_expand "ashlsi3"    [(set (match_operand:SI            0 "s_register_operand" "")          (ashift:SI (match_operand:SI 1 "s_register_operand" "") @@ -4130,12 +4112,6 @@      {        rtx scratch1, scratch2;   -      if (operands[2] == CONST1_RTX (SImode)) -        { -          emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1])); -          DONE; -        } -        /* Ideally we should use iwmmxt here if we could know that operands[1]           ends up already living in an iwmmxt register. Otherwise it's           cheaper to have the alternate code being generated than moving @@ -4152,18 +4128,6 @@    "  )   -(define_insn "arm_ashrdi3_1bit" -  [(set (match_operand:DI              0 "s_register_operand" "=r,&r") -        (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") -                     (const_int 1))) -   (clobber (reg:CC CC_REGNUM))] -  "TARGET_32BIT" -  "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" -  [(set_attr "conds" "clob") -   (set_attr "length" "8") -   (set_attr "type" "multiple")] -) -  (define_expand "ashrsi3"    [(set (match_operand:SI              0 "s_register_operand" "")          (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") @@ -4196,12 +4160,6 @@      {        rtx scratch1, scratch2;   -      if (operands[2] == CONST1_RTX (SImode)) -        { -          emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1])); -          DONE; -        } -        /* Ideally we should use iwmmxt here if we could know that operands[1]           ends up already living in an iwmmxt register. Otherwise it's           cheaper to have the alternate code being generated than moving @@ -4218,18 +4176,6 @@    "  )   -(define_insn "arm_lshrdi3_1bit" -  [(set (match_operand:DI              0 "s_register_operand" "=r,&r") -        (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") -                     (const_int 1))) -   (clobber (reg:CC CC_REGNUM))] -  "TARGET_32BIT" -  "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" -  [(set_attr "conds" "clob") -   (set_attr "length" "8") -   (set_attr "type" "multiple")] -) -  (define_expand "lshrsi3"    [(set (match_operand:SI              0 "s_register_operand" "")          (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "") diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index cf281df0292d0f511d7d63e828886d860a3a8201..ebac36db8db3a74a16cc4ef7f76b1edd90e28fc9 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1184,12 +1184,8 @@          gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])                      || REGNO (operands[0]) == REGNO (operands[1]));   -       if (operands[2] == CONST1_RTX (SImode)) -         /* This clobbers CC.  */ -         emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1])); -       else -         arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], -                                        operands[2], operands[3], operands[4]); +       arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], +                                      operands[2], operands[3], operands[4]);        }      DONE;    }" @@ -1288,13 +1284,9 @@          gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])                      || REGNO (operands[0]) == REGNO (operands[1]));   -       if (operands[2] == CONST1_RTX (SImode)) -         /* This clobbers CC.  */ -         emit_insn (gen_arm_di3_1bit (operands[0], operands[1])); -       else -         /* This clobbers CC (ASHIFTRT by register only).  */ -         arm_emit_coreregs_64bit_shift (, operands[0], operands[1], -                                  operands[2], operands[3], operands[4]); +       /* This clobbers CC (ASHIFTRT by register only).  */ +       arm_emit_coreregs_64bit_shift (, operands[0], operands[1], +                                      operands[2], operands[3], operands[4]);        }        DONE;