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[ARM] Improve Thumb allocation order

Message ID AM5PR0802MB2610099277743B6FD1E05137839A0@AM5PR0802MB2610.eurprd08.prod.outlook.com
State New
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Commit Message

Wilco Dijkstra Dec. 14, 2016, 4:39 p.m. UTC 
ping


From: Wilco Dijkstra
Sent: 30 November 2016 17:32
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Improve Thumb allocation order
    
Thumb uses a special register allocation order to increase the use of low
registers.  Oddly enough, LR appears before R12, which means that LR must
be saved and restored even if R12 is available.  Swapping R12 and LR means
this simple example now uses R12 as a temporary (just like ARM):

int f(long long a, long long b)
{
  if (a < b) return 1;
  return a + b;
}

        cmp     r0, r2
        sbcs    ip, r1, r3
        ite     ge
        addge   r0, r0, r2
        movlt   r0, #1
        bx      lr

Bootstrap OK. CSibe benchmarks unchanged.

ChangeLog:
2016-11-30  Wilco Dijkstra  <wdijkstr@arm.com>

        * gcc/config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14.

--
diff mbox

Patch

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 43c78f6148a5306fb0079ee2eba12f3763652bcc..29dcefd23762ba861b458b8860eb4b4856a9cb02 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -26455,7 +26455,7 @@  arm_mangle_type (const_tree type)
 static const int thumb_core_reg_alloc_order[] =
 {
    3,  2,  1,  0,  4,  5,  6,  7,
-  14, 12,  8,  9, 10, 11
+  12, 14,  8,  9, 10, 11
 };
 
 /* Adjust register allocation order when compiling for Thumb.  */