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Fri, 11 Nov 2016 13:14:18 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM5PR0802MB2609.eurprd08.prod.outlook.com (10.175.46.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.721.10; Fri, 11 Nov 2016 13:14:15 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.0721.010; Fri, 11 Nov 2016 13:14:15 +0000 From: Wilco Dijkstra To: Richard Earnshaw , GCC Patches CC: nd Subject: Re: [PATCH][AArch64] Improve TI mode address offsets Date: Fri, 11 Nov 2016 13:14:15 +0000 Message-ID: References: , <5ba4a624-d159-c66d-ac16-d6c60f68b2bf@foss.arm.com> In-Reply-To: <5ba4a624-d159-c66d-ac16-d6c60f68b2bf@foss.arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-microsoft-exchange-diagnostics: 1; AM5PR0802MB2609; 7:1Eq57ToxOcY1RUpvGha3jYOvlCRMNNER6sUoI4xGQg3lAuAMFufcZELhpIdufDFbWnvBk8b5PVNUPd+BuMYN3uk5bV1aw56oVGqrw2lyTxWEMZYlaMmF8EImUOtnN5zAChcvsSxQiCeByH3Q70zumvaUlSdR6WXrjw2jcp383pgro/Qd9FwLnNrSW5q6H35rM462vb8i71zscNx4VZkuChFNFOL+YBlf0zAxcmJZzMJXRiZXaCY3D+phMPK6CKfpJ3KU/IDyZJxFsUANHo0vOgFbguJ1VGt5WtefmDRm8ATOLLrH++Cr92UAjdAoIVn5rhl5UovK9CAMFOzcbQQA/SHr8KZiuiufPvLJ26rd84s= x-ms-office365-filtering-correlation-id: d56c6592-0ccf-4371-f1c2-08d40a34a318 x-microsoft-antispam: UriScan:; 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FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Nov 2016 13:14:15.5499 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2609 Richard Earnshaw wrote: > Has this patch been truncated?  The last line above looks to be part-way > through a hunk. Oops sorry, it seems the last few lines are missing. Here is the full version: diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3045e6d6447d5c1860feb51708eeb2a21d2caca9..45f44e96ba9e9d3c8c41d977aa509fa13398a8fd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4066,7 +4066,8 @@ aarch64_classify_address (struct aarch64_address_info *info, instruction memory accesses. */ if (mode == TImode || mode == TFmode) return (aarch64_offset_7bit_signed_scaled_p (DImode, offset) - && offset_9bit_signed_unscaled_p (mode, offset)); + && (offset_9bit_signed_unscaled_p (mode, offset) + || offset_12bit_unsigned_scaled_p (mode, offset))); /* A 7bit offset check because OImode will emit a ldp/stp instruction (only big endian will get here). @@ -4270,18 +4271,19 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x, /* Split an out-of-range address displacement into a base and offset. Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise to increase opportunities for sharing the base address of different sizes. - For TI/TFmode and unaligned accesses use a 256-byte range. */ + For unaligned accesses and TI/TF mode use the signed 9-bit range. */ static bool aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode) { - HOST_WIDE_INT mask = GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3fff; + HOST_WIDE_INT offset = INTVAL (*disp); + HOST_WIDE_INT base = offset & ~(GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3ffc); - if (mode == TImode || mode == TFmode || - (INTVAL (*disp) & (GET_MODE_SIZE (mode) - 1)) != 0) - mask = 0xff; + if (mode == TImode || mode == TFmode + || (offset & (GET_MODE_SIZE (mode) - 1)) != 0) + base = (offset + 0x100) & ~0x1ff; - *off = GEN_INT (INTVAL (*disp) & ~mask); - *disp = GEN_INT (INTVAL (*disp) & mask); + *off = GEN_INT (base); + *disp = GEN_INT (offset - base); return true; } @@ -5148,12 +5150,10 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode) x = gen_rtx_PLUS (Pmode, base, offset_rtx); } - /* Does it look like we'll need a load/store-pair operation? */ + /* Does it look like we'll need a 16-byte load/store-pair operation? */ HOST_WIDE_INT base_offset; - if (GET_MODE_SIZE (mode) > 16 - || mode == TImode) - base_offset = ((offset + 64 * GET_MODE_SIZE (mode)) - & ~((128 * GET_MODE_SIZE (mode)) - 1)); + if (GET_MODE_SIZE (mode) > 16) + base_offset = (offset + 0x400) & ~0x7f0; /* For offsets aren't a multiple of the access size, the limit is -256...255. */ else if (offset & (GET_MODE_SIZE (mode) - 1)) @@ -5167,6 +5167,8 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode) /* Small negative offsets are supported. */ else if (IN_RANGE (offset, -256, 0)) base_offset = 0; + else if (mode == TImode || mode == TFmode) + base_offset = (offset + 0x100) & ~0x1ff; /* Use 12-bit offset by access size. */ else base_offset = offset & (~0xfff * GET_MODE_SIZE (mode)); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 24b7288976dd0452f41475e40f02750fc56a2a20..62eda569f9b642ac569a61718d7debf7eae1b59e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1094,9 +1094,9 @@ (define_insn "*movti_aarch64" [(set (match_operand:TI 0 - "nonimmediate_operand" "=r, *w,r ,*w,r ,Ump,Ump,*w,m") + "nonimmediate_operand" "=r, *w,r ,*w,r,m,m,*w,m") (match_operand:TI 1 - "aarch64_movti_operand" " rn,r ,*w,*w,Ump,r ,Z , m,*w"))] + "aarch64_movti_operand" " rn,r ,*w,*w,m,r,Z, m,*w"))] "(register_operand (operands[0], TImode) || aarch64_reg_or_zero (operands[1], TImode))" "@ @@ -1211,9 +1211,9 @@ (define_insn "*movtf_aarch64" [(set (match_operand:TF 0 - "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump") + "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r,m ,m") (match_operand:TF 1 - "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,Ump,?r ,Y"))] + "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,m ,?r,Y"))] "TARGET_FLOAT && (register_operand (operands[0], TFmode) || aarch64_reg_or_fp_zero (operands[1], TFmode))" "@