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SFV:NSPM; SFS:(10019020)(98900003); DIR:OUT; SFP:1102; SCL:1; SRVR:DB5EUR03HT229; H:AM4PR0701MB2162.eurprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; x-ms-office365-filtering-correlation-id: 518e2dd8-6aed-4355-79bc-08d3e9062d2b x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(1601124038)(1603103081)(1601125047); SRVR:DB5EUR03HT229; x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(432015012)(102415321)(82015046); SRVR:DB5EUR03HT229; BCL:0; PCL:0; RULEID:; SRVR:DB5EUR03HT229; x-forefront-prvs: 008184426E spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2016 07:48:32.5210 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5EUR03HT229 Hi, this patch mitigates the excessive stack usage on arm in code that does lots of int64 shift ops like sha512. It reduces the stack usage in that example from 4K to 2K while less than 0.5K would be expected. In all cases the additional set instructions are optimized later so that this caused no code size increase, but just made LRA's job a bit easier. It does certainly not solve the problem completely but at least improve the stability, in an area that I'd call security relevant. Boot-strapped and reg-tested on arm-linux-gnueabihf. Is it OK for trunk? Thanks Bernd. 2016-09-29 Bernd Edlinger PR target/77308 * config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result register explicitly. Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 239624) +++ gcc/config/arm/arm.c (working copy) @@ -29159,6 +29159,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, /* Shifts by a constant less than 32. */ rtx reverse_amount = GEN_INT (32 - INTVAL (amount)); + emit_insn (SET (out, const0_rtx)); emit_insn (SET (out_down, LSHIFT (code, in_down, amount))); emit_insn (SET (out_down, ORR (REV_LSHIFT (code, in_up, reverse_amount), @@ -29170,12 +29171,11 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, /* Shifts by a constant greater than 31. */ rtx adj_amount = GEN_INT (INTVAL (amount) - 32); + emit_insn (SET (out, const0_rtx)); emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount))); if (code == ASHIFTRT) emit_insn (gen_ashrsi3 (out_up, in_up, GEN_INT (31))); - else - emit_insn (SET (out_up, const0_rtx)); } } else