From patchwork Fri Apr 22 14:24:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 613678 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qryZM2sNxz9sCk for ; Sat, 23 Apr 2016 00:25:14 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Ds+5y989; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=TTJxwkePQ9O/CR60 9dNM//7DzOrQIWjvzM6CUxxF08mlz6FCuuY81WoItp/M52uycMnHGdy/S1P1vd1L rY2JX6yQ6Ps/tqoG2YXl6aw/Qm5EjqyzxZAkEpsHMGrtOuxLwDsVb0wDTfoUeCP0 u6H5rPIMQLA9dvTgAiNpwi905yA= DKIM-Signature: v=1; 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Fri, 22 Apr 2016 14:24:55 +0000 Received: from emea01-am1-obe.outbound.protection.outlook.com (mail-am1lrp0010.outbound.protection.outlook.com [213.199.154.10]) (Using TLS) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-47-Z_Wv6foER9i9SIWWNz9e6w-1; Fri, 22 Apr 2016 15:24:50 +0100 Received: from AM3PR08MB0088.eurprd08.prod.outlook.com (2a01:111:e400:8847::18) by AM3PR08MB0088.eurprd08.prod.outlook.com (2a01:111:e400:8847::18) with Microsoft SMTP Server (TLS) id 15.1.466.19; Fri, 22 Apr 2016 14:24:49 +0000 Received: from AM3PR08MB0088.eurprd08.prod.outlook.com ([fe80::d0af:2d98:cf1b:e43e]) by AM3PR08MB0088.eurprd08.prod.outlook.com ([fe80::d0af:2d98:cf1b:e43e%17]) with mapi id 15.01.0466.023; Fri, 22 Apr 2016 14:24:49 +0000 From: Wilco Dijkstra To: "gcc-patches@gcc.gnu.org" CC: nd Subject: [PATCH][AArch64] print_operand should not fallthrough from register operand into generic operand Date: Fri, 22 Apr 2016 14:24:49 +0000 Message-ID: x-ms-office365-filtering-correlation-id: 008783d5-bc0d-449c-f61e-08d36ab9dcef x-microsoft-exchange-diagnostics: 1; AM3PR08MB0088; 5:HStdK3lixmxTe7BlmBNDRpOpfp6VAs8Nlq+hi5djzX2AUJoiIsiSPcy62lm7OjWeghHsUaU9i4ZBW0KfoV1BnPwvywtxgAtv1dOEp1kwKCSsm0pfXHAEbotk/ZuCmw9Ge5mgIDf5NnfzJexnXQVA1lZsNThQ1hwy1ebFqszJQtFvmISb0ZQjTWnR2JbVwID8; 24:VBG429N3el+ysllM8bECrAAiFQKUzft8Gker3FntQB4u8bLJQQE1FpAQ65t42PwQs9rLVPy/vXYOd8aA2XOW3SUWJGcYIZkabbAGVN72SDw=; 7:xeC3C5gbVvB+gDjGQ7Ikna5HiNEAfxDpyCaHm7fp9II6x1QTBtqiBJx8WZcyAUV7MYZv5puRKV83PtzmLaXKtb2kiMzmfTUzpDe6AxRiim0el4g4RHlExUUiUE+YVSijPas+U/PHy1OTftQowXcu+WZdvQkhu5E1KlCVqZ3z3PPfpHcQIJudwk8Z7Mtw/ngMqKdOWFe2L0UPcAibDWqi/GrIUZmCpotJmhzsaMX4ZRQ=; 20:/vSSkTyvZS2oifg+0Ys8+TWbIluyzzkmwKrRIGAmkQjZNNrRLfpm0SllsUOSCTs9L3GvOyjkcOo0iLpoYR9ehqXMwbDd5pu0FC8bs3Bw06tE2MHSFUVjqe9BkOaE+I7VCNN1AQDUW44gbLOZIPoym3P/YoirFEmqAv/+C05YppI= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM3PR08MB0088; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(9101521026)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001); SRVR:AM3PR08MB0088; BCL:0; PCL:0; RULEID:; SRVR:AM3PR08MB0088; x-forefront-prvs: 0920602B08 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(377424004)(5250100002)(2501003)(3280700002)(87936001)(575784001)(92566002)(66066001)(19580395003)(19580405001)(5003600100002)(450100001)(5002640100001)(33656002)(106116001)(86362001)(5008740100001)(54356999)(9686002)(1220700001)(6116002)(2906002)(11100500001)(1096002)(102836003)(74316001)(586003)(2900100001)(3846002)(110136002)(81166005)(3660700001)(189998001)(50986999)(15975445007)(2351001)(4326007)(5004730100002)(229853001)(41533002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0088; H:AM3PR08MB0088.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2016 14:24:49.5860 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0088 X-MC-Unique: Z_Wv6foER9i9SIWWNz9e6w-1 Some patterns are using '%w2' for immediate operands, which means that a zero immediate is actually emitted as 'wzr' or 'xzr'. This not only changes an immediate operand into a register operand but may emit illegal instructions from legal RTL (eg. ORR x0, SP, xzr rather than ORR x0, SP, 0). Remove the fallthrough in aarch64_print_operand from the 'w' and 'x' case into the '0' case that created this issue. Modify a few patterns to use '%2' rather than '%w2' for an immediate or memory operand so they now print correctly without the fallthrough. OK for trunk? (note this requires https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01265.html to be committed first) ChangeLog: 2016-04-22 Wilco Dijkstra gcc/ * config/aarch64/aarch64.md (add3_compareC_cconly_imm): Remove use of %w for immediate. (add3_compareC_imm): Likewise. (si3_uxtw): Split into register and immediate variants. (andsi3_compare0_uxtw): Likewise. (and3_compare0): Likewise. (and3nr_compare0): Likewise. (stack_protect_test_): Don't use %x for memory operands. * config/aarch64/aarch64.c (aarch64_print_operand): Remove fallthrough from 'w' and 'x' case into '0' case. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 881dc52e2de03231abb217a9ce22cbb1cc44bc6c..bcef50825c8315c39e29dbe57c387ea2a4fe445d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4608,7 +4608,8 @@ aarch64_print_operand (FILE *f, rtx x, int code) break; } - /* Fall through */ + output_operand_lossage ("invalid operand for '%%%c'", code); + return; case 0: /* Print a normal operand, if it's a general register, then we diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3e474bb0939c5786a181b67173c62ada73c4bd82..60a20366d16fb1d4eccb43ac32cfc1f0e6096cd0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1779,7 +1779,7 @@ "aarch64_zero_extend_const_eq (mode, operands[2], mode, operands[1])" "@ - cmn\\t%0, %1 + cmn\\t%0, %1 cmp\\t%0, #%n1" [(set_attr "type" "alus_imm")] ) @@ -1811,7 +1811,7 @@ "aarch64_zero_extend_const_eq (mode, operands[3], mode, operands[2])" "@ - adds\\t%0, %1, %2 + adds\\t%0, %1, %2 subs\\t%0, %1, #%n2" [(set_attr "type" "alus_imm")] ) @@ -3418,7 +3418,9 @@ (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r") (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] "" - "\\t%w0, %w1, %w2" + "@ + \\t%w0, %w1, %w2 + \\t%w0, %w1, %2" [(set_attr "type" "logic_reg,logic_imm")] ) @@ -3431,7 +3433,9 @@ (set (match_operand:GPI 0 "register_operand" "=r,r") (and:GPI (match_dup 1) (match_dup 2)))] "" - "ands\\t%0, %1, %2" + "@ + ands\\t%0, %1, %2 + ands\\t%0, %1, %2" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -3445,7 +3449,9 @@ (set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] "" - "ands\\t%w0, %w1, %w2" + "@ + ands\\t%w0, %w1, %w2 + ands\\t%w0, %w1, %2" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -3799,7 +3805,9 @@ (match_operand:GPI 1 "aarch64_logical_operand" "r,")) (const_int 0)))] "" - "tst\\t%0, %1" + "@ + tst\\t%0, %1 + tst\\t%0, %1" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -5187,7 +5195,7 @@ UNSPEC_SP_TEST)) (clobber (match_scratch:PTR 3 "=&r"))] "" - "ldr\t%3, %x1\;ldr\t%0, %x2\;eor\t%0, %3, %0" + "ldr\t%3, %1\;ldr\t%0, %2\;eor\t%0, %3, %0" [(set_attr "length" "12") (set_attr "type" "multiple")])