diff mbox

[AArch64] print_operand should not fallthrough from register operand into generic operand

Message ID AM3PR08MB00888C00CA43FC4314E28CEC83640@AM3PR08MB0088.eurprd08.prod.outlook.com
State New
Headers show

Commit Message

Wilco Dijkstra April 27, 2016, 4:39 p.m. UTC 
James Greenhalgh wrote:
> So the part of this patch removing the fallthrough to general operand
> is not OK for trunk.
>
> The other parts look reasonable to me, please resubmit just those.

Right, I removed the removal of the fallthrough. Here is the revised version:

ChangeLog:
2016-04-27  Wilco Dijkstra  <wdijkstr@arm.com>

gcc/
	* config/aarch64/aarch64.md
	(add<mode>3_compareC_cconly_imm): Remove use of %w.
	(add<mode>3_compareC_imm): Likewise.
	(<optab>si3_uxtw): Split into register and immediate variants.
	(andsi3_compare0_uxtw): Likewise.
	(and<mode>3_compare0): Likewise.
	(and<mode>3nr_compare0): Likewise.
	(stack_protect_test_<mode>): Don't use %x for memory operands.

--

Comments

James Greenhalgh May 16, 2016, 11:21 a.m. UTC | #1 
On Wed, Apr 27, 2016 at 05:39:33PM +0100, Wilco Dijkstra wrote:
> James Greenhalgh wrote:
> > So the part of this patch removing the fallthrough to general operand
> > is not OK for trunk.
> >
> > The other parts look reasonable to me, please resubmit just those.
> 
> Right, I removed the removal of the fallthrough. Here is the revised version:

OK.

Thanks,
James

> 
> ChangeLog:
> 2016-04-27  Wilco Dijkstra  <wdijkstr@arm.com>
> 
> gcc/
> 	* config/aarch64/aarch64.md
> 	(add<mode>3_compareC_cconly_imm): Remove use of %w.
> 	(add<mode>3_compareC_imm): Likewise.
> 	(<optab>si3_uxtw): Split into register and immediate variants.
> 	(andsi3_compare0_uxtw): Likewise.
> 	(and<mode>3_compare0): Likewise.
> 	(and<mode>3nr_compare0): Likewise.
> 	(stack_protect_test_<mode>): Don't use %x for memory operands.
>
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 19981c205d3e2a6102510647bde9b29906a4fdc9..4e41b3b0f5b2369431ffec1a0029af53fc5aebd9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1755,7 +1755,7 @@ 
   "aarch64_zero_extend_const_eq (<DWI>mode, operands[2],
 				 <MODE>mode, operands[1])"
   "@
-  cmn\\t%<w>0, %<w>1
+  cmn\\t%<w>0, %1
   cmp\\t%<w>0, #%n1"
   [(set_attr "type" "alus_imm")]
 )
@@ -1787,11 +1787,11 @@ 
   "aarch64_zero_extend_const_eq (<DWI>mode, operands[3],
                                  <MODE>mode, operands[2])"
   "@
-  adds\\t%<w>0, %<w>1, %<w>2
+  adds\\t%<w>0, %<w>1, %2
   subs\\t%<w>0, %<w>1, #%n2"
   [(set_attr "type" "alus_imm")]
 )
- 
+
 (define_insn "add<mode>3_compareC"
   [(set (reg:CC_C CC_REGNUM)
 	(ne:CC_C
@@ -3394,7 +3394,9 @@ 
          (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r")
 		     (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))]
   ""
-  "<logical>\\t%w0, %w1, %w2"
+  "@
+   <logical>\\t%w0, %w1, %w2
+   <logical>\\t%w0, %w1, %2"
   [(set_attr "type" "logic_reg,logic_imm")]
 )
 
@@ -3407,7 +3409,9 @@ 
    (set (match_operand:GPI 0 "register_operand" "=r,r")
 	(and:GPI (match_dup 1) (match_dup 2)))]
   ""
-  "ands\\t%<w>0, %<w>1, %<w>2"
+  "@
+   ands\\t%<w>0, %<w>1, %<w>2
+   ands\\t%<w>0, %<w>1, %2"
   [(set_attr "type" "logics_reg,logics_imm")]
 )
 
@@ -3421,7 +3425,9 @@ 
    (set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
   ""
-  "ands\\t%w0, %w1, %w2"
+  "@
+   ands\\t%w0, %w1, %w2
+   ands\\t%w0, %w1, %2"
   [(set_attr "type" "logics_reg,logics_imm")]
 )
 
@@ -3775,7 +3781,9 @@ 
 		  (match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
 	 (const_int 0)))]
   ""
-  "tst\\t%<w>0, %<w>1"
+  "@
+   tst\\t%<w>0, %<w>1
+   tst\\t%<w>0, %1"
   [(set_attr "type" "logics_reg,logics_imm")]
 )
 
@@ -5170,7 +5178,7 @@ 
 	 UNSPEC_SP_TEST))
    (clobber (match_scratch:PTR 3 "=&r"))]
   ""
-  "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
+  "ldr\t%<w>3, %1\;ldr\t%<w>0, %2\;eor\t%<w>0, %<w>3, %<w>0"
   [(set_attr "length" "12")
    (set_attr "type" "multiple")])