From patchwork Sat Aug 28 08:57:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingjie Xing X-Patchwork-Id: 62899 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 98F40B711E for ; Sat, 28 Aug 2010 18:57:51 +1000 (EST) Received: (qmail 11008 invoked by alias); 28 Aug 2010 08:57:49 -0000 Received: (qmail 11000 invoked by uid 22791); 28 Aug 2010 08:57:48 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-yx0-f175.google.com (HELO mail-yx0-f175.google.com) (209.85.213.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 28 Aug 2010 08:57:44 +0000 Received: by yxk30 with SMTP id 30so1694590yxk.20 for ; Sat, 28 Aug 2010 01:57:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.145.11 with SMTP id s11mr1823526ybd.203.1282985862041; Sat, 28 Aug 2010 01:57:42 -0700 (PDT) Received: by 10.150.182.8 with HTTP; Sat, 28 Aug 2010 01:57:42 -0700 (PDT) Date: Sat, 28 Aug 2010 16:57:42 +0800 Message-ID: Subject: [mips] Change the definition of macro SHIFT_COUNT_TRUNCATED From: Mingjie Xing To: gcc-patches@gcc.gnu.org X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello, This patch change the definition of macro SHIFT_COUNT_TRUNCATED. This can fix the bug on Loongson for such an test case, /* { dg-do run } */ /* { dg-options "isa=loongson -mhard-float -mno-mips16 -O1" } */ #include "loongson.h" #include typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t; void main1 (int shift) { int32x2_encap_t s; int32x2_encap_t r; s.a[0] = 0xffffffff; s.a[1] = 0xffffffff; /* Loongson SIMD use low-order 7 bits to specify the shift amount. Thus V2SI << 0x40 == 0. The below expression 'shift & 0x3f' will be mis-optimized as 'shift', if SHIFT_COUNT_TRUNCATED is nonzero. */ r.v = psllw_s (s.v, (shift & 0x3f)); assert (r.a[0] == 0xffffffff); assert (r.a[1] == 0xffffffff); } int main (void) { main1 (0x40); return 0; } ChangeLog: 2010-08-28 Mingjie Xing * config/mips/mips.h (SHIFT_COUNT_TRUNCATED) : Define to 0 for Loongson targets, 1 otherwise. Is it OK? BTW, I'm not sure if I should commit the test case. Thanks, Mingjie Index: config/mips/mips.h =================================================================== --- config/mips/mips.h (revision 163612) +++ config/mips/mips.h (working copy) @@ -2422,8 +2422,11 @@ typedef struct mips_args { #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) /* Define this to be nonzero if shift instructions ignore all but the low-order - few bits. */ -#define SHIFT_COUNT_TRUNCATED 1 + few bits. + + For Loongson targets, the Loongson specific vector shift instructions are + not SHIFT_COUNT_TRUNCATED. */ +#define SHIFT_COUNT_TRUNCATED (TARGET_LOONGSON_2EF ? 0 : 1) /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */