From patchwork Sun Jan 2 02:12:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingjie Xing X-Patchwork-Id: 77176 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 5C03AB70B3 for ; Sun, 2 Jan 2011 13:12:54 +1100 (EST) Received: (qmail 21432 invoked by alias); 2 Jan 2011 02:12:51 -0000 Received: (qmail 21422 invoked by uid 22791); 2 Jan 2011 02:12:50 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-wy0-f175.google.com (HELO mail-wy0-f175.google.com) (74.125.82.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 02 Jan 2011 02:12:45 +0000 Received: by wyb40 with SMTP id 40so12846625wyb.20 for ; Sat, 01 Jan 2011 18:12:43 -0800 (PST) MIME-Version: 1.0 Received: by 10.227.144.12 with SMTP id x12mr10783776wbu.102.1293934362444; Sat, 01 Jan 2011 18:12:42 -0800 (PST) Received: by 10.227.42.12 with HTTP; Sat, 1 Jan 2011 18:12:42 -0800 (PST) Date: Sun, 2 Jan 2011 10:12:42 +0800 Message-ID: Subject: [PATCH MIPS][LS3A] Add the pipeline description for Loongson3A From: Mingjie Xing To: gcc-patches@gcc.gnu.org Cc: Mingming Sun X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch add the pipeline description for Loongson3A. Tested on 3A machine. Is it OK? 2011-01-02 Mingjie Xing * config/mips/loongson3a.md: New file. * config/mips/mips.md: Include loongson3a.md. * config/mips/mips.c (mips_multipass_dfa_lookahead): Return 4 when TUNE_LOONGSON_3A. Thanks, Mingjie Index: config/mips/loongson3a.md =================================================================== --- config/mips/loongson3a.md (revision 0) +++ config/mips/loongson3a.md (revision 0) @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson-3A cores. + +;; Copyright (C) 2011 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "ls3a_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "ls3a_a_falu") + +;; Automaton for memory operations. +(define_automaton "ls3a_a_mem") + +;; Describe the resources. + +(define_cpu_unit "ls3a_alu1" "ls3a_a_alu") +(define_cpu_unit "ls3a_alu2" "ls3a_a_alu") +(define_cpu_unit "ls3a_mem" "ls3a_a_mem") +(define_cpu_unit "ls3a_falu1" "ls3a_a_falu") +(define_cpu_unit "ls3a_falu2" "ls3a_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "ls3a_arith" 1 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "ls3a_alu1 | ls3a_alu2") + +(define_insn_reservation "ls3a_branch" 1 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "ls3a_alu1") + +(define_insn_reservation "ls3a_mfhilo" 1 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "mfhilo,mthilo")) + "ls3a_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "ls3a_imul3nc" 5 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "imul3nc")) + "ls3a_alu2") + +(define_insn_reservation "ls3a_imul" 7 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "imul,imadd")) + "ls3a_alu2 * 7") + +(define_insn_reservation "ls3a_idiv_si" 12 + (and (eq_attr "cpu" "loongson_3a") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "ls3a_alu2 * 12") + +(define_insn_reservation "ls3a_idiv_di" 25 + (and (eq_attr "cpu" "loongson_3a") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "ls3a_alu2 * 25") + +(define_insn_reservation "ls3a_load" 3 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "load")) + "ls3a_mem") + +(define_insn_reservation "ls3a_fpload" 4 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "load,mfc,mtc")) + "ls3a_mem") + +(define_insn_reservation "ls3a_prefetch" 0 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "prefetch,prefetchx")) + "ls3a_mem") + +(define_insn_reservation "ls3a_store" 0 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "store,fpstore,fpidxstore")) + "ls3a_mem") + +;; All the fp operations can be executed in FAUL1. Only fp add, +;; sub, mul, madd can be executed in FAUL2. Try FAUL2 firstly. +(define_insn_reservation "ls3a_fadd" 6 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "fadd,fmul,fmadd")) + "ls3a_falu2 | ls3a_falu1") + +(define_insn_reservation "ls3a_fcmp" 2 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "ls3a_falu1") + +(define_insn_reservation "ls3a_fcvt" 4 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "fcvt")) + "ls3a_falu1") + +(define_insn_reservation "ls3a_fdiv_sf" 12 + (and (eq_attr "cpu" "loongson_3a") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "ls3a_falu1 * 12") + +(define_insn_reservation "ls3a_fdiv_df" 19 + (and (eq_attr "cpu" "loongson_3a") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "ls3a_falu1 * 19") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "ls3a_unknown" 1 + (and (eq_attr "cpu" "loongson_3a") + (eq_attr "type" "unknown,multi")) + "ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem") + +;; End of DFA-based pipeline description for loongson_3a Index: config/mips/mips.md =================================================================== --- config/mips/mips.md (revision 168079) +++ config/mips/mips.md (working copy) @@ -908,6 +908,7 @@ (include "9000.md") (include "10000.md") (include "loongson2ef.md") +(include "loongson3a.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") Index: config/mips/mips.c =================================================================== --- config/mips/mips.c (revision 168079) +++ config/mips/mips.c (working copy) @@ -12154,7 +12154,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF) + if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) return 4; if (TUNE_OCTEON)