From patchwork Mon Dec 20 21:25:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 76231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id CF246B70AF for ; Tue, 21 Dec 2010 08:26:13 +1100 (EST) Received: (qmail 9417 invoked by alias); 20 Dec 2010 21:26:09 -0000 Received: (qmail 9405 invoked by uid 22791); 20 Dec 2010 21:26:07 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-pv0-f175.google.com (HELO mail-pv0-f175.google.com) (74.125.83.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 20 Dec 2010 21:26:02 +0000 Received: by pvd12 with SMTP id 12so754466pvd.20 for ; Mon, 20 Dec 2010 13:26:00 -0800 (PST) MIME-Version: 1.0 Received: by 10.143.40.1 with SMTP id s1mr3849231wfj.379.1292880359981; Mon, 20 Dec 2010 13:25:59 -0800 (PST) Received: by 10.142.252.8 with HTTP; Mon, 20 Dec 2010 13:25:59 -0800 (PST) In-Reply-To: <4D0FC4B3.6040107@redhat.com> References: <4D0FC4B3.6040107@redhat.com> Date: Mon, 20 Dec 2010 22:25:59 +0100 Message-ID: Subject: Re: Fix 64-bit Solaris 2/x86 IE TLS code sequence (PR target/43309) From: Uros Bizjak To: Richard Henderson Cc: Rainer Orth , gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Mon, Dec 20, 2010 at 10:03 PM, Richard Henderson wrote: > On 12/20/2010 11:26 AM, Uros Bizjak wrote: >> +       /* The SUN linker took the AMD64 TLS spec literally >> +          and can only handle %rax as destination of the >> +          initial executable code sequence.  */ >> + >> +       rtx rax = gen_rtx_REG (Pmode, AX_REG); > > It's much better not to use an explicit hard register > and instead rely on the 'a' constraint in the pattern. IIRC, there were certain problems with reload trying to allocate %rax to the pattern. Anyway, attached patch also generates correct code for my small tests. Rainer, can you please test attached patch? Uros. Index: i386.c =================================================================== --- i386.c (revision 168050) +++ i386.c (working copy) @@ -12571,7 +12571,21 @@ legitimize_tls_address (rtx x, enum tls_ off = gen_const_mem (Pmode, off); set_mem_alias_set (off, ix86_GOT_alias_set ()); - if (TARGET_64BIT || TARGET_ANY_GNU_TLS) + if (TARGET_64BIT && TARGET_SUN_TLS) + { + /* The SUN linker took the AMD64 TLS spec literally + and can only handle %rax as destination of the + initial executable code sequence. */ + + dest = gen_reg_rtx (Pmode); + + base = get_thread_pointer (false); + emit_insn (gen_rtx_SET (VOIDmode, dest, base)); + emit_insn (gen_add_tls_addr_di_sun (dest, dest, off)); + + return dest; + } + else if (TARGET_64BIT || TARGET_ANY_GNU_TLS) { base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS); off = force_reg (Pmode, off); Index: i386.md =================================================================== --- i386.md (revision 168050) +++ i386.md (working copy) @@ -93,6 +93,7 @@ UNSPEC_TLS_GD UNSPEC_TLS_LD_BASE UNSPEC_TLSDESC + UNSPEC_TLSDESC_SUN ;; Other random patterns UNSPEC_SCAS @@ -12661,6 +12664,31 @@ ;; Segment register for the thread base ptr load (define_mode_attr tp_seg [(SI "gs") (DI "fs")]) +;; The SUN linker took the AMD64 TLS spec literally and can only handle +;; %rax as the destination of the initial executable code sequence. +(define_insn "*load_tp_di_sun" + [(set (match_operand:DI 0 "register_operand" "=a") + (unspec:DI [(const_int 0)] UNSPEC_TP))] + "TARGET_64BIT && TARGET_SUN_TLS" + "mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}" + [(set_attr "type" "imov") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + +(define_insn "add_tls_addr_di_sun" + [(set (match_operand:DI 0 "register_operand" "=a") + (plus:DI + (match_operand:DI 1 "register_operand" "0") + (match_operand:DI 2 "memory_operand" "m"))) + (clobber (reg:CC FLAGS_REG)) + (unspec [(const_int 0)] UNSPEC_TLSDESC_SUN)] + "TARGET_64BIT && TARGET_SUN_TLS" + "add{q}\t{%2, %0|%0, %2}"; + [(set_attr "type" "alu") + (set_attr "mode" "DI")]) + ;; Load and add the thread base pointer from %gs:0. (define_insn "*load_tp_" [(set (match_operand:P 0 "register_operand" "=r")