From patchwork Wed Aug 11 01:13:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Carrot Wei X-Patchwork-Id: 61421 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 9D22DB70A6 for ; Wed, 11 Aug 2010 11:14:00 +1000 (EST) Received: (qmail 29005 invoked by alias); 11 Aug 2010 01:13:57 -0000 Received: (qmail 28954 invoked by uid 22791); 11 Aug 2010 01:13:56 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (216.239.44.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 11 Aug 2010 01:13:51 +0000 Received: from wpaz5.hot.corp.google.com (wpaz5.hot.corp.google.com [172.24.198.69]) by smtp-out.google.com with ESMTP id o7B1Dn7O015373 for ; Tue, 10 Aug 2010 18:13:49 -0700 Received: from gwaa20 (gwaa20.prod.google.com [10.200.27.20]) by wpaz5.hot.corp.google.com with ESMTP id o7B1DlRs019736 for ; Tue, 10 Aug 2010 18:13:48 -0700 Received: by gwaa20 with SMTP id a20so5690476gwa.37 for ; Tue, 10 Aug 2010 18:13:47 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.197.14 with SMTP id u14mr13145036ybf.372.1281489227082; Tue, 10 Aug 2010 18:13:47 -0700 (PDT) Received: by 10.151.129.10 with HTTP; Tue, 10 Aug 2010 18:13:46 -0700 (PDT) In-Reply-To: <1281349800.5172.9.camel@e102346-lin.cambridge.arm.com> References: <1281349800.5172.9.camel@e102346-lin.cambridge.arm.com> Date: Wed, 11 Aug 2010 09:13:46 +0800 Message-ID: Subject: Re: [PATCH: PR target/44999] Replace "and r0, r0, #255" with uxtb in thumb2 From: Carrot Wei To: Richard Earnshaw Cc: gcc-patches@gcc.gnu.org X-System-Of-Record: true Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi Richard The following patch has been modified as your suggestion. And it passed the testing on qemu. On Mon, Aug 9, 2010 at 6:30 PM, Richard Earnshaw wrote: > > On Thu, 2010-07-22 at 15:11 +0800, Carrot Wei wrote: >> In thumb2 "and r0, r0, #255" is 32 bit, uxtb is 16 bit and does the same >> operation. This patch simply detect the situation in pattern "andsi3" and call >> gen_thumb2_zero_extendqisi2_v6. > >> Index: arm.md >> =================================================================== >> --- arm.md      (revision 162396) >> +++ arm.md      (working copy) >> @@ -1933,9 +1933,16 @@ >>      { >>        if (GET_CODE (operands[2]) == CONST_INT) >>          { >> -          arm_split_constant (AND, SImode, NULL_RTX, >> -                             INTVAL (operands[2]), operands[0], >> -                             operands[1], optimize && can_create_pseudo_p ()); >> +         if (INTVAL (operands[2]) == 255 && arm_arch6) >> +           { >> +             operands[1] = gen_rtx_SUBREG (QImode, operands[1], 0); > > No, never generate SUBREGs directly like this (you get the wrong byte > for a big-endian core). > > Instead, you should use convert_to_mode(). > >>+/* { dg-options "-march=armv7-a -mthumb -Os" }  */ >>+/* { dg-final { scan-assembler "uxtb" } } */ > > This is also wrong and will break if people are testing other CPU > permutations.  See thumb2-cmpneg2add-1.c for an example of how to do > this correctly. > > R. > > Index: pr44999.c =================================================================== --- pr44999.c (revision 0) +++ pr44999.c (revision 0) @@ -0,0 +1,9 @@ +/* Use UXTB to extract the lowest byte. */ +/* { dg-options "-mthumb -Os" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "uxtb" } } */ + +int tp(int x, int y) +{ + return (x & 0xff) - (y & 0xffff); +} Index: thumb2.md =================================================================== --- thumb2.md (revision 163046) +++ thumb2.md (working copy) @@ -907,7 +907,7 @@ (set_attr "neg_pool_range" "*,250")] ) -(define_insn "*thumb2_zero_extendqisi2_v6" +(define_insn "thumb2_zero_extendqisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "TARGET_THUMB2 && arm_arch6" Index: arm.md =================================================================== --- arm.md (revision 163046) +++ arm.md (working copy) @@ -1947,9 +1947,17 @@ { if (GET_CODE (operands[2]) == CONST_INT) { - arm_split_constant (AND, SImode, NULL_RTX, - INTVAL (operands[2]), operands[0], - operands[1], optimize && can_create_pseudo_p ()); + if (INTVAL (operands[2]) == 255 && arm_arch6) + { + operands[1] = convert_to_mode (QImode, operands[1], 1); + emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0], + operands[1])); + } + else + arm_split_constant (AND, SImode, NULL_RTX, + INTVAL (operands[2]), operands[0], + operands[1], + optimize && can_create_pseudo_p ()); DONE; }