From patchwork Mon Jan 9 12:00:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Toma Tabacu X-Patchwork-Id: 712627 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3txtzC5CGPz9s5g for ; Mon, 9 Jan 2017 23:01:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="UzeWsMFQ"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=CtV nRjD5BtnvFZ2MNGPCB/XyCWvD2cG4XEoNqEe5Qpg+47fOUlH9ujEFYs5p2Ohj7VQ uat2tEyqzZv8kMOe0Ce4XpruyIaDabC0oSN7/oXw3iVPt4eVoTh3o/GC4ZWDcUQg bZNedsPXUqxQBYgPj1om6XuDba8amM6SMR4S2xmw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=442hcGp+8 RKc2OH9rId0qAODgc0=; b=UzeWsMFQ03dYdZw2mKfVh7XKOZrQKeVNE72nFN2yx seikY/8z7jgwfHvG9hPH/75EgVGbPiqsyPBP25xtt8xFsNpozJtO0Xa4HB37QEko 1L2NuwXcHIx5FjtE/gPZwH/v/jmHk2528MDN6lAVv+FaqqZ/PQZ22fYruwsFi28A 40= Received: (qmail 65093 invoked by alias); 9 Jan 2017 12:01:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65080 invoked by uid 89); 9 Jan 2017 12:01:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=toma, sk:!TARGET, UD:G X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Jan 2017 12:00:54 +0000 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id E4D9B45F4D31E; Mon, 9 Jan 2017 12:00:48 +0000 (GMT) Received: from HHMAIL01.hh.imgtec.org ([fe80::710b:f219:72bc:e0b3]) by hhmail02.hh.imgtec.org ([fe80::5400:d33e:81a4:f775%25]) with mapi id 14.03.0294.000; Mon, 9 Jan 2017 12:00:51 +0000 From: Toma Tabacu To: "gcc-patches@gcc.gnu.org" CC: Matthew Fortune , "catherine_moore@mentor.com" Subject: [PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets. Date: Mon, 9 Jan 2017 12:00:50 +0000 Message-ID: MIME-Version: 1.0 X-IsSubscribed: yes Hi, The expand_DIVMOD function, introduced in r241660, will pick the divmod4 (or the udivmod4) pattern when it checks for the presence of hardware div/mod instructions, which results in the generation of the old DIV instruction. Unfortunately, this interferes with the generation of DIV.G and MOD.G (the div3 and mod3 patterns) for Loongson targets, which causes test failures. This patch prevents the selection of divmod4 and udivmod4 when targeting Loongson by adding !ISA_HAS_DIV3 to the match condition. ISA_HAS_DIV3 checks for the presence of the 3-operand Loongson-specific DIV.G and MOD.G instructions. Tested with mips-mti-elf. This solution might be excessive, however, as it effectively forbids the generation of the old DIV instruction for Loongson targets, which actually do support it. Is this OK ? Regards, Toma gcc/ChangeLog: * config/mips/mips.md (divmod4): Add check for !ISA_HAS_DIV3. (udivmod4): Likewise. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 076cde6..f2fedcc 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2851,7 +2851,7 @@ (set (match_operand:GPR 3 "register_operand") (mod:GPR (match_dup 1) (match_dup 2)))])] - "ISA_HAS_DIV && !TARGET_FIX_VR4120" + "ISA_HAS_DIV && !TARGET_FIX_VR4120 && !ISA_HAS_DIV3" { if (TARGET_MIPS16) { @@ -2916,7 +2916,7 @@ (set (match_operand:GPR 3 "register_operand") (umod:GPR (match_dup 1) (match_dup 2)))])] - "ISA_HAS_DIV && !TARGET_FIX_VR4120" + "ISA_HAS_DIV && !TARGET_FIX_VR4120 && !ISA_HAS_DIV3" { if (TARGET_MIPS16) {