@@ -438,6 +438,8 @@ enum aarch64_builtins
/* Special cased Armv8.3-A Complex FMA by Lane quad Builtins. */
AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS
+ /* Builtin for Arm8.3-a Javascript conversion instruction. */
+ AARCH64_JSCVT,
/* TME builtins. */
AARCH64_TME_BUILTIN_TSTART,
AARCH64_TME_BUILTIN_TCOMMIT,
@@ -1150,6 +1152,12 @@ aarch64_init_builtins (void)
aarch64_init_builtin_rsqrt ();
aarch64_init_rng_builtins ();
+ tree ftype_jcvt
+ = build_function_type_list (intSI_type_node, double_type_node, NULL);
+ aarch64_builtin_decls[AARCH64_JSCVT]
+ = add_builtin_function ("__builtin_aarch64_jcvtzs", ftype_jcvt,
+ AARCH64_JSCVT, BUILT_IN_MD, NULL, NULL_TREE);
+
/* Initialize pointer authentication builtins which are backed by instructions
in NOP encoding space.
@@ -1739,6 +1747,16 @@ aarch64_expand_builtin (tree exp,
return target;
+ case AARCH64_JSCVT:
+ arg0 = CALL_EXPR_ARG (exp, 0);
+ op0 = force_reg (DFmode, expand_normal (arg0));
+ if (!target)
+ target = gen_reg_rtx (SImode);
+ else
+ target = force_reg (SImode, target);
+ emit_insn (GEN_FCN (CODE_FOR_aarch64_fjcvtzs) (target, op0));
+ return target;
+
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF:
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF:
case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF:
@@ -110,6 +110,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_CRC32, "__ARM_FEATURE_CRC32", pfile);
aarch64_def_or_undef (TARGET_DOTPROD, "__ARM_FEATURE_DOTPROD", pfile);
aarch64_def_or_undef (TARGET_COMPLEX, "__ARM_FEATURE_COMPLEX", pfile);
+ aarch64_def_or_undef (TARGET_JSCVT, "__ARM_FEATURE_JCVT", pfile);
cpp_undef (pfile, "__AARCH64_CMODEL_TINY__");
cpp_undef (pfile, "__AARCH64_CMODEL_SMALL__");
@@ -289,6 +289,9 @@ extern unsigned aarch64_architecture_version;
/* ARMv8.3-A features. */
#define TARGET_ARMV8_3 (AARCH64_ISA_V8_3)
+/* Javascript conversion instruction from Armv8.3-a. */
+#define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3)
+
/* Armv8.3-a Complex number extension to AdvSIMD extensions. */
#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
@@ -141,6 +141,7 @@
UNSPEC_CRC32X
UNSPEC_FCVTZS
UNSPEC_FCVTZU
+ UNSPEC_FJCVTZS
UNSPEC_FRINT32Z
UNSPEC_FRINT32X
UNSPEC_FRINT64Z
@@ -6925,6 +6926,15 @@
[(set_attr "length" "0")]
)
+(define_insn "aarch64_fjcvtzs"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:DF 1 "register_operand" "w")]
+ UNSPEC_FJCVTZS))]
+ "TARGET_JSCVT"
+ "fjcvtzs\\t%w0, %d1"
+ [(set_attr "type" "f_cvtf2i")]
+)
+
;; Pointer authentication patterns are always provided. In architecture
;; revisions prior to ARMv8.3-A these HINT instructions operate as NOPs.
;; This lets the user write portable software which authenticates pointers
@@ -130,6 +130,16 @@ __ttest (void)
#pragma GCC pop_options
#endif
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.3-a")
+__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+__jcvt (double __a)
+{
+ return __builtin_aarch64_jcvtzs (__a);
+}
+
+#pragma GCC pop_options
+
#pragma GCC push_options
#pragma GCC target ("arch=armv8.5-a")
__extension__ static __inline float __attribute__ ((__always_inline__))
new file mode 100644
@@ -0,0 +1,15 @@
+/* Test the __jcvt ACLE intrinsic. */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.3-a" } */
+
+#include <arm_acle.h>
+
+#ifdef __ARM_FEATURE_JCVT
+int32_t
+test_jcvt (double a)
+{
+ return __jcvt (a);
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */