From patchwork Wed Sep 28 05:30:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1683684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=NfIZs94N; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MclTn3hK3z202k for ; Wed, 28 Sep 2022 15:31:23 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 476703857C4B for ; Wed, 28 Sep 2022 05:31:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 476703857C4B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1664343079; bh=mf5JIq2gMElG/+BtBlDRARvnEIDK662YWuVo8cYu8fk=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=NfIZs94N/47P8axZ6vk26QXIMRnTgKXt92ma6BKVFsqUwgYKnqttSOgz+da1XkbfV /YD4zAnNavDxNns2al5dkyMN69jC4cuLrF6piemgBdFWSgfijs5RTMvD4WHroArrG/ JpRxzA4Jrx/hsvLzwhqyv4X0TORHoDrL+CxCjvMk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id AEA993858D28 for ; Wed, 28 Sep 2022 05:30:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AEA993858D28 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28S4RKrn007533; Wed, 28 Sep 2022 05:30:58 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3jvf8r9ame-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Sep 2022 05:30:57 +0000 Received: from m0098417.ppops.net (m0098417.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28S5P23X002904; Wed, 28 Sep 2022 05:30:57 GMT Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3jvf8r9akp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Sep 2022 05:30:57 +0000 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 28S5LVIH024035; Wed, 28 Sep 2022 05:30:55 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma04ams.nl.ibm.com with ESMTP id 3juapujcrn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Sep 2022 05:30:55 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 28S5QcxD44958030 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 28 Sep 2022 05:26:38 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EE2BE42045; Wed, 28 Sep 2022 05:30:52 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC57642041; Wed, 28 Sep 2022 05:30:50 +0000 (GMT) Received: from [9.197.236.18] (unknown [9.197.236.18]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 28 Sep 2022 05:30:50 +0000 (GMT) Message-ID: <9d9f1f43-b528-387d-45a7-1d89400de0fc@linux.ibm.com> Date: Wed, 28 Sep 2022 13:30:46 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Content-Language: en-US To: GCC Patches Subject: [PATCH] rs6000: Rework option -mpowerpc64 handling [PR106680] X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: u5MVBCbGXmiBfnkBF3sjjvsYZCecv7Dj X-Proofpoint-GUID: u8Zd5PF2OYcykM4cqs4UNV3rYyoCBDLo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-28_02,2022-09-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 clxscore=1011 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209280030 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Peter Bergner , iain@sandoe.co.uk, David Edelsohn , Segher Boessenkool , idsandoe@googlemail.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, PR106680 shows that -m32 -mpowerpc64 is different from -mpowerpc64 -m32, this is determined by the way how we handle option powerpc64 in rs6000_handle_option. Segher pointed out this difference should be taken as a bug and we should ensure that option powerpc64 is independent of -m32/-m64. So this patch removes the handlings in rs6000_handle_option and add some necessary supports in rs6000_option_override_internal instead. With this patch, if users specify -m{no-,}powerpc64, the specified value is honoured, otherwise, for 64bit it always enables OPTION_MASK_POWERPC64 while for 32bit it disables OPTION_MASK_POWERPC64 if OS_MISSING_POWERPC64. Bootstrapped and regress-tested on: - powerpc64-linux-gnu P7 and P8 {-m64,-m32} - powerpc64le-linux-gnu P9 and P10 - powerpc-ibm-aix7.2.0.0 {-maix64,-maix32} Hi Iain, could you help to test this on darwin to ensure it won't break darwin's build and new tests are fine? Thanks in advance! Is it ok for trunk if darwin testing goes well? BR, Kewen ----- PR target/106680 gcc/ChangeLog: * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): Remove the adjustment for option powerpc64 in -m64 handling, and remove the whole -m32 handling. * config/rs6000/rs6000.cc (rs6000_option_override_internal): When no explicit powerpc64 option is provided, enable it at -m64 and disable it for OS_MISSING_POWERPC64. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr106680-1.c: New test. * gcc.target/powerpc/pr106680-2.c: New test. * gcc.target/powerpc/pr106680-3.c: New test. * gcc.target/powerpc/pr106680-4.c: New test. --- gcc/common/config/rs6000/rs6000-common.cc | 11 ------- gcc/config/rs6000/rs6000.cc | 33 ++++++++++++++----- gcc/testsuite/gcc.target/powerpc/pr106680-1.c | 12 +++++++ gcc/testsuite/gcc.target/powerpc/pr106680-2.c | 13 ++++++++ gcc/testsuite/gcc.target/powerpc/pr106680-3.c | 12 +++++++ gcc/testsuite/gcc.target/powerpc/pr106680-4.c | 16 +++++++++ 6 files changed, 77 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106680-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106680-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106680-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106680-4.c -- 2.27.0 diff --git a/gcc/common/config/rs6000/rs6000-common.cc b/gcc/common/config/rs6000/rs6000-common.cc index 8e393d08a23..c76b5c27bb6 100644 --- a/gcc/common/config/rs6000/rs6000-common.cc +++ b/gcc/common/config/rs6000/rs6000-common.cc @@ -119,19 +119,8 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, #else case OPT_m64: #endif - opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags & OPTION_MASK_PPC_GFXOPT); - opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; - break; - -#ifdef TARGET_USES_AIX64_OPT - case OPT_maix32: -#else - case OPT_m32: -#endif - opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; - opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e6fa3ad0eb7..605d35893f9 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3648,17 +3648,12 @@ rs6000_option_override_internal (bool global_init_p) rs6000_pointer_size = 32; } - /* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, - we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; - if the user wants either, the user must explicitly specify them and we - won't interfere with the user's specification. */ + /* Some OSs don't support saving Altivec registers. On those OSs, we don't + touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; if the + user wants either, the user must explicitly specify them and we won't + interfere with the user's specification. */ set_masks = POWERPC_MASKS; -#ifdef OS_MISSING_POWERPC64 - if (OS_MISSING_POWERPC64) - set_masks &= ~OPTION_MASK_POWERPC64; -#endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX @@ -3753,6 +3748,26 @@ rs6000_option_override_internal (bool global_init_p) error ("AltiVec not supported in this target"); } + /* With option powerpc64 specified explicitly (either on or off), even if + being compiled for 64 bit we don't need to check if it's disabled here, + since subtargets will check and raise an error message if necessary + later. But without option powerpc64 specified explicitly, we need to + ensure powerpc64 enabled for 64 bit and disabled on those OSes with + OS_MISSING_POWERPC64, since they don't support saving the high part of + 64-bit registers on context switch. */ + if (!(rs6000_isa_flags_explicit & OPTION_MASK_POWERPC64)) + { + if (TARGET_64BIT) + /* Make sure we always enable it by default for 64 bit. */ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; +#ifdef OS_MISSING_POWERPC64 + else if (OS_MISSING_POWERPC64) + /* It's unexpected to have OPTION_MASK_POWERPC64 on for OSes which + miss powerpc64 support, so disable it. */ + rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; +#endif + } + /* If we are optimizing big endian systems for space, use the load/store multiple instructions. */ if (BYTES_BIG_ENDIAN && optimize_size) diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c new file mode 100644 index 00000000000..ff33f6864c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c @@ -0,0 +1,12 @@ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mno-powerpc64" } */ + +/* Verify there is an error message about PowerPC64 requirement. */ + +int foo () +{ + return 1; +} + +/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target powerpc*-*-linux* powerpc-*-rtems* } 0 } */ +/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled" "PR106680" { target powerpc*-*-aix* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c new file mode 100644 index 00000000000..25439910c27 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c @@ -0,0 +1,13 @@ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mno-powerpc64 -m64" } */ + +/* Verify option -m64 doesn't override option -mno-powerpc64, + and there is an error message about PowerPC64 requirement. */ + +int foo () +{ + return 1; +} + +/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target powerpc*-*-linux* powerpc-*-rtems* } 0 } */ +/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled" "PR106680" { target powerpc*-*-aix* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c new file mode 100644 index 00000000000..f8eea8ea645 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c @@ -0,0 +1,12 @@ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-m64 -mno-powerpc64" } */ + +/* Verify there is an error message about PowerPC64 requirement. */ + +int foo () +{ + return 1; +} + +/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target powerpc*-*-linux* powerpc-*-rtems* } 0 } */ +/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled" "PR106680" { target powerpc*-*-aix* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-4.c b/gcc/testsuite/gcc.target/powerpc/pr106680-4.c new file mode 100644 index 00000000000..bfbdd8eb0b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106680-4.c @@ -0,0 +1,16 @@ +/* Skip this on aix, otherwise it emits the error message like "64-bit + computation with 32-bit addressing not yet supported" on aix. */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-mpowerpc64 -m32 -O2" } */ + +/* Verify option -m32 doesn't override option -mpowerpc64. + If option -mpowerpc64 gets overridden, the assembly would + end up with addc and adde. */ +/* { dg-final { scan-assembler-not "addc" } } */ +/* { dg-final { scan-assembler-not "adde" } } */ + +long long foo (long long a, long long b) +{ + return a+b; +}