From patchwork Fri May 5 09:41:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1777520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss-cipunited-com.20200927.dkim.feishu.cn header.i=@oss-cipunited-com.20200927.dkim.feishu.cn header.a=rsa-sha256 header.s=s1 header.b=F+cOpcsi; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QCQjR0SSWz20fg for ; Fri, 5 May 2023 19:43:23 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ADFA93889809 for ; Fri, 5 May 2023 09:43:11 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.18]) by sourceware.org (Postfix) with UTF8SMTPS id 129AE3853808 for ; Fri, 5 May 2023 09:41:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 129AE3853808 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683279712; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=6GMqcDIytkIcyhdwp4HadPS1uV/h+YGnfduG9A2A/As=; b=F+cOpcsiDovFhrKuycQeszuQCzNgllL2F80nghevkD/6Wsc88fxaOnfCHMgUKVS9PX6P2n tC3jIYAt/jP46QjIDNnqm7mJ0N54tzRJvPcX+4yfQOcYMgOcl18KxUgtAahMQYKBSVetw2 pc+5JJKRBkSUOhZaWqpVJzCVrEjmQFp4En4fdODsAIAGh7nNBZJ5kSMpRbpZO1XMwCvoRY DaXmQRjQlrc5EcUJBgNbvQqBRXFEM0i7B/f3XvE4tXuG82DXMfwdpwMW3S7DwVLEg7HGG3 vnz+qzQxsguD7ljbtBDVrDbVq1gvxXGuqBid2W0ZQGWzcqA2MA7PTGzv/tRRqg== Subject: [PATCH 8/8] MIPS: Add CACHE instruction for mips16e2 X-Mailer: git-send-email 2.40.1 References: Date: Fri, 05 May 2023 17:41:40 +0800 Message-Id: <9c80bb4c48610f82a6ffd2966c2c800909fb6f81.1683273172.git.jie.mei@oss.cipunited.com> Mime-Version: 1.0 X-Lms-Return-Path: To: From: "Jie Mei" In-Reply-To: X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, HTML_MESSAGE, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above. (AVAIL_NON_MIPS16 (cache..)): Update to AVAIL_MIPS16E2_OR_NON_MIPS16. * config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md (mips_cache): Mark as extended MIPS16. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cache.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 25 ++++++++++++-- gcc/config/mips/mips.h | 3 +- gcc/config/mips/mips.md | 3 +- .../gcc.target/mips/mips16e2-cache.c | 34 +++++++++++++++++++ 4 files changed, 60 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 275efc5a390..e6f4701ad3a 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2845,6 +2845,9 @@ mips_9bit_offset_address_p (rtx x, machine_mode mode) return (mips_classify_address (&addr, x, mode, false) && addr.type == ADDRESS_REG && CONST_INT_P (addr.offset) + && (!TARGET_MIPS16E2 + || M16_REG_P (REGNO (addr.reg)) + || REGNO (addr.reg) >= FIRST_PSEUDO_REGISTER) && MIPS_9BIT_OFFSET_P (INTVAL (addr.offset))); } @@ -15412,9 +15415,13 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx) The function is available on the current target if !TARGET_MIPS16. BUILTIN_AVAIL_MIPS16 - The function is available on the current target if TARGET_MIPS16. */ + The function is available on the current target if TARGET_MIPS16. + + BUILTIN_AVAIL_MIPS16E2 + The function is available on the current target if TARGET_MIPS16E2. */ #define BUILTIN_AVAIL_NON_MIPS16 1 #define BUILTIN_AVAIL_MIPS16 2 +#define BUILTIN_AVAIL_MIPS16E2 4 /* Declare an availability predicate for built-in functions that require non-MIPS16 mode and also require COND to be true. @@ -15426,6 +15433,17 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx) return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ } +/* Declare an availability predicate for built-in functions that + require non-MIPS16 mode or MIPS16E2 and also require COND to be true. + NAME is the main part of the predicate's name. */ +#define AVAIL_MIPS16E2_OR_NON_MIPS16(NAME, COND) \ + static unsigned int \ + mips_builtin_avail_##NAME (void) \ + { \ + return ((COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16E2 \ + : 0); \ + } + /* Declare an availability predicate for built-in functions that support both MIPS16 and non-MIPS16 code and also require COND to be true. NAME is the main part of the predicate's name. */ @@ -15471,7 +15489,7 @@ AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI) -AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) +AVAIL_MIPS16E2_OR_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) AVAIL_NON_MIPS16 (msa, TARGET_MSA) /* Construct a mips_builtin_description from the given arguments. @@ -17471,7 +17489,8 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, d = &mips_builtins[fcode]; avail = d->avail (); gcc_assert (avail != 0); - if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)) + if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16) + && (!TARGET_MIPS16E2 || !(avail & BUILTIN_AVAIL_MIPS16E2))) { error ("built-in function %qE not supported for MIPS16", DECL_NAME (fndecl)); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 1947be25aca..207b8871b12 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1385,7 +1385,8 @@ struct mips_cpu_info { #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) /* The CACHE instruction is available. */ -#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) +#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && (!TARGET_MIPS16 \ + || TARGET_MIPS16E2)) /* Tell collect what flags to pass to nm. */ #ifndef NM_FLAGS diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 5ef8d99d99c..7eb65891820 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5751,7 +5751,8 @@ (match_operand:QI 1 "address_operand" "ZD")] UNSPEC_MIPS_CACHE))] "ISA_HAS_CACHE" - "cache\t%X0,%a1") + "cache\t%X0,%a1" + [(set_attr "extended_mips16" "yes")]) ;; Similar, but with the operands hard-coded to an R10K cache barrier ;; operation. We keep the pattern distinct so that we can identify diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c new file mode 100644 index 00000000000..dcc39b580f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c @@ -0,0 +1,34 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16 -mmips16e2" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* Test cache. */ + +void +test01 (int *area) +{ + __builtin_mips_cache (20, area); +} + +void +test02 (const short *area) +{ + __builtin_mips_cache (24, area + 10); +} + +void +test03 (volatile unsigned int *area, int offset) +{ + __builtin_mips_cache (0, area + offset); +} + +void +test04 (const volatile unsigned char *area) +{ + __builtin_mips_cache (4, area - 80); +} + +/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */ +