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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id y10-20020a1c4b0a000000b003f91e32b1ebsm1547842wma.17.2023.07.05.02.13.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Jul 2023 02:13:13 -0700 (PDT) Message-ID: <9b896dcc-1612-22c6-6770-12159c9b1f07@gmail.com> Date: Wed, 5 Jul 2023 11:13:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches , palmer , Kito Cheng , "juzhe.zhong@rivai.ai" , jeffreyalaw Subject: [PATCH] RISC-V: Support variable index in vec_extract. X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, this patch adds a gen_lowpart in the vec_extract expander so it properly works with a variable index and adds tests. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md: Add gen_lowpart. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Add tests for variable index. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c: Ditto. --- gcc/config/riscv/autovec.md | 1 + .../rvv/autovec/vls-vlmax/vec_extract-1.c | 33 +++- .../rvv/autovec/vls-vlmax/vec_extract-2.c | 32 +++- .../rvv/autovec/vls-vlmax/vec_extract-3.c | 32 +++- .../rvv/autovec/vls-vlmax/vec_extract-4.c | 32 +++- .../rvv/autovec/vls-vlmax/vec_extract-run.c | 154 ++++++------------ .../autovec/vls-vlmax/vec_extract-zvfh-run.c | 49 +++--- 7 files changed, 171 insertions(+), 162 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 6ee1af7990e..466b27d5c49 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1088,6 +1088,7 @@ (define_expand "vec_extract" { /* Emit the slide down to index 0 in a new vector. */ tmp = gen_reg_rtx (mode); + operands[2] = gen_lowpart (Pmode, operands[2]); rtx ops[] = {tmp, RVV_VUNDEF (mode), operands[1], operands[2]}; riscv_vector::emit_vlmax_slide_insn (code_for_pred_slide (UNSPEC_VSLIDEDOWN, mode), ops); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c index 9cb167a8cdc..34a82128042 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c @@ -11,7 +11,6 @@ typedef _Float16 vnx8hf __attribute__((vector_size (16))); typedef float vnx4sf __attribute__((vector_size (16))); typedef double vnx2df __attribute__((vector_size (16))); - #define VEC_EXTRACT(S,V,IDX) \ S \ __attribute__((noipa)) \ @@ -20,6 +19,14 @@ typedef double vnx2df __attribute__((vector_size (16))); return v[IDX]; \ } +#define VEC_EXTRACT_VAR1(S,V) \ + S \ + __attribute__((noipa)) \ + vec_extract_var_##V (V v, int8_t idx) \ + { \ + return v[idx]; \ + } + #define TEST_ALL1(T) \ T (_Float16, vnx8hf, 0) \ T (_Float16, vnx8hf, 3) \ @@ -43,17 +50,27 @@ typedef double vnx2df __attribute__((vector_size (16))); T (int8_t, vnx16qi, 11) \ T (int8_t, vnx16qi, 15) \ +#define TEST_ALL_VAR1(T) \ + T (_Float16, vnx8hf) \ + T (float, vnx4sf) \ + T (double, vnx2df) \ + T (int64_t, vnx2di) \ + T (int32_t, vnx4si) \ + T (int16_t, vnx8hi) \ + T (int8_t, vnx16qi) \ + TEST_ALL1 (VEC_EXTRACT) +TEST_ALL_VAR1 (VEC_EXTRACT_VAR1) -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*ta,\s*ma} 5 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*ta,\s*ma} 6 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*ta,\s*ma} 6 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*ta,\s*ma} 4 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*ta,\s*ma} 6 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*ta,\s*ma} 8 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*ta,\s*ma} 8 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*ta,\s*ma} 6 } } */ /* { dg-final { scan-assembler-times {\tvslidedown.vi} 14 } } */ -/* { dg-final { scan-assembler-times {\tvslidedown.vx} 0 } } */ +/* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */ -/* { dg-final { scan-assembler-times {\tvfmv.f.s} 8 } } */ -/* { dg-final { scan-assembler-times {\tvmv.x.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tvfmv.f.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tvmv.x.s} 17 } } */ /* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c index 2837ff58e2d..4288a6d2411 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c @@ -19,6 +19,14 @@ typedef double vnx4df __attribute__((vector_size (32))); return v[IDX]; \ } +#define VEC_EXTRACT_VAR2(S,V) \ + S \ + __attribute__((noipa)) \ + vec_extract_var_##V (V v, int16_t idx) \ + { \ + return v[idx]; \ + } + #define TEST_ALL2(T) \ T (_Float16, vnx16hf, 0) \ T (_Float16, vnx16hf, 3) \ @@ -54,17 +62,27 @@ typedef double vnx4df __attribute__((vector_size (32))); T (int8_t, vnx32qi, 16) \ T (int8_t, vnx32qi, 31) \ +#define TEST_ALL_VAR2(T) \ + T (_Float16, vnx16hf) \ + T (float, vnx8sf) \ + T (double, vnx4df) \ + T (int64_t, vnx4di) \ + T (int32_t, vnx8si) \ + T (int16_t, vnx16hi) \ + T (int8_t, vnx32qi) \ + TEST_ALL2 (VEC_EXTRACT) +TEST_ALL_VAR2 (VEC_EXTRACT_VAR2) -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m2,\s*ta,\s*ma} 5 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m2,\s*ta,\s*ma} 10 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m2,\s*ta,\s*ma} 10 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m2,\s*ta,\s*ma} 8 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m2,\s*ta,\s*ma} 6 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m2,\s*ta,\s*ma} 12 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m2,\s*ta,\s*ma} 12 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m2,\s*ta,\s*ma} 10 } } */ /* { dg-final { scan-assembler-times {\tvslidedown.vi} 26 } } */ -/* { dg-final { scan-assembler-times {\tvslidedown.vx} 0 } } */ +/* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */ -/* { dg-final { scan-assembler-times {\tvfmv.f.s} 14 } } */ -/* { dg-final { scan-assembler-times {\tvmv.x.s} 19 } } */ +/* { dg-final { scan-assembler-times {\tvfmv.f.s} 17 } } */ +/* { dg-final { scan-assembler-times {\tvmv.x.s} 23 } } */ /* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c index 47f30ed79f1..0102848656a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c @@ -19,6 +19,14 @@ typedef double vnx8df __attribute__((vector_size (64))); return v[IDX]; \ } +#define VEC_EXTRACT_VAR3(S,V) \ + S \ + __attribute__((noipa)) \ + vec_extract_var_##V (V v, int32_t idx) \ + { \ + return v[idx]; \ + } + #define TEST_ALL3(T) \ T (_Float16, vnx32hf, 0) \ T (_Float16, vnx32hf, 3) \ @@ -55,17 +63,27 @@ typedef double vnx8df __attribute__((vector_size (64))); T (int8_t, vnx64qi, 32) \ T (int8_t, vnx64qi, 63) \ +#define TEST_ALL_VAR3(T) \ + T (_Float16, vnx32hf) \ + T (float, vnx16sf) \ + T (double, vnx8df) \ + T (int64_t, vnx8di) \ + T (int32_t, vnx16si) \ + T (int16_t, vnx32hi) \ + T (int8_t, vnx64qi) \ + TEST_ALL3 (VEC_EXTRACT) +TEST_ALL_VAR3 (VEC_EXTRACT_VAR3) -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m4,\s*ta,\s*ma} 5 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m4,\s*ta,\s*ma} 11 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m4,\s*ta,\s*ma} 10 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m4,\s*ta,\s*ma} 8 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m4,\s*ta,\s*ma} 6 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m4,\s*ta,\s*ma} 13 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m4,\s*ta,\s*ma} 12 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m4,\s*ta,\s*ma} 10 } } */ /* { dg-final { scan-assembler-times {\tvslidedown.vi} 25 } } */ -/* { dg-final { scan-assembler-times {\tvslidedown.vx} 2 } } */ +/* { dg-final { scan-assembler-times {\tvslidedown.vx} 9 } } */ -/* { dg-final { scan-assembler-times {\tvfmv.f.s} 15 } } */ -/* { dg-final { scan-assembler-times {\tvmv.x.s} 19 } } */ +/* { dg-final { scan-assembler-times {\tvfmv.f.s} 18 } } */ +/* { dg-final { scan-assembler-times {\tvmv.x.s} 23 } } */ /* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c index f7169f07506..d8deb7dc3ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c @@ -19,6 +19,14 @@ typedef double vnx16df __attribute__((vector_size (128))); return v[IDX]; \ } +#define VEC_EXTRACT_VAR4(S,V) \ + S \ + __attribute__((noipa)) \ + vec_extract_var_##V (V v, int64_t idx) \ + { \ + return v[idx]; \ + } + #define TEST_ALL4(T) \ T (_Float16, vnx64hf, 0) \ T (_Float16, vnx64hf, 3) \ @@ -58,17 +66,27 @@ typedef double vnx16df __attribute__((vector_size (128))); T (int8_t, vnx128qi, 64) \ T (int8_t, vnx128qi, 127) \ +#define TEST_ALL_VAR4(T) \ + T (_Float16, vnx64hf) \ + T (float, vnx32sf) \ + T (double, vnx16df) \ + T (int64_t, vnx16di) \ + T (int32_t, vnx32si) \ + T (int16_t, vnx64hi) \ + T (int8_t, vnx128qi) \ + TEST_ALL4 (VEC_EXTRACT) +TEST_ALL_VAR4 (VEC_EXTRACT_VAR4) -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m8,\s*ta,\s*ma} 6 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m8,\s*ta,\s*ma} 13 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m8,\s*ta,\s*ma} 10 } } */ -/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m8,\s*ta,\s*ma} 8 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m8,\s*ta,\s*ma} 7 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m8,\s*ta,\s*ma} 15 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m8,\s*ta,\s*ma} 12 } } */ +/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m8,\s*ta,\s*ma} 10 } } */ /* { dg-final { scan-assembler-times {\tvslidedown.vi} 23 } } */ -/* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */ +/* { dg-final { scan-assembler-times {\tvslidedown.vx} 14 } } */ -/* { dg-final { scan-assembler-times {\tvfmv.f.s} 17 } } */ -/* { dg-final { scan-assembler-times {\tvmv.x.s} 20 } } */ +/* { dg-final { scan-assembler-times {\tvfmv.f.s} 20 } } */ +/* { dg-final { scan-assembler-times {\tvmv.x.s} 24 } } */ /* { dg-final { scan-assembler-not {\tsext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c index 43110c0bb8d..c5ee2701a03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c @@ -18,117 +18,25 @@ void check_##V##_##IDX () \ assert (res == v[IDX]); \ } -#define CHECK_ALL(T) \ - T (float, vnx4sf, 0) \ - T (float, vnx4sf, 1) \ - T (float, vnx4sf, 3) \ - T (double, vnx2df, 0) \ - T (double, vnx2df, 1) \ - T (int64_t, vnx2di, 0) \ - T (int64_t, vnx2di, 1) \ - T (int32_t, vnx4si, 0) \ - T (int32_t, vnx4si, 1) \ - T (int32_t, vnx4si, 3) \ - T (int16_t, vnx8hi, 0) \ - T (int16_t, vnx8hi, 2) \ - T (int16_t, vnx8hi, 6) \ - T (int8_t, vnx16qi, 0) \ - T (int8_t, vnx16qi, 1) \ - T (int8_t, vnx16qi, 7) \ - T (int8_t, vnx16qi, 11) \ - T (int8_t, vnx16qi, 15) \ - T (float, vnx8sf, 0) \ - T (float, vnx8sf, 1) \ - T (float, vnx8sf, 3) \ - T (float, vnx8sf, 4) \ - T (float, vnx8sf, 7) \ - T (double, vnx4df, 0) \ - T (double, vnx4df, 1) \ - T (double, vnx4df, 2) \ - T (double, vnx4df, 3) \ - T (int64_t, vnx4di, 0) \ - T (int64_t, vnx4di, 1) \ - T (int64_t, vnx4di, 2) \ - T (int64_t, vnx4di, 3) \ - T (int32_t, vnx8si, 0) \ - T (int32_t, vnx8si, 1) \ - T (int32_t, vnx8si, 3) \ - T (int32_t, vnx8si, 4) \ - T (int32_t, vnx8si, 7) \ - T (int16_t, vnx16hi, 0) \ - T (int16_t, vnx16hi, 1) \ - T (int16_t, vnx16hi, 7) \ - T (int16_t, vnx16hi, 8) \ - T (int16_t, vnx16hi, 15) \ - T (int8_t, vnx32qi, 0) \ - T (int8_t, vnx32qi, 1) \ - T (int8_t, vnx32qi, 15) \ - T (int8_t, vnx32qi, 16) \ - T (int8_t, vnx32qi, 31) \ - T (float, vnx16sf, 0) \ - T (float, vnx16sf, 2) \ - T (float, vnx16sf, 6) \ - T (float, vnx16sf, 8) \ - T (float, vnx16sf, 14) \ - T (double, vnx8df, 0) \ - T (double, vnx8df, 2) \ - T (double, vnx8df, 4) \ - T (double, vnx8df, 6) \ - T (int64_t, vnx8di, 0) \ - T (int64_t, vnx8di, 2) \ - T (int64_t, vnx8di, 4) \ - T (int64_t, vnx8di, 6) \ - T (int32_t, vnx16si, 0) \ - T (int32_t, vnx16si, 2) \ - T (int32_t, vnx16si, 6) \ - T (int32_t, vnx16si, 8) \ - T (int32_t, vnx16si, 14) \ - T (int16_t, vnx32hi, 0) \ - T (int16_t, vnx32hi, 2) \ - T (int16_t, vnx32hi, 14) \ - T (int16_t, vnx32hi, 16) \ - T (int16_t, vnx32hi, 30) \ - T (int8_t, vnx64qi, 0) \ - T (int8_t, vnx64qi, 2) \ - T (int8_t, vnx64qi, 30) \ - T (int8_t, vnx64qi, 32) \ - T (int8_t, vnx64qi, 63) \ - T (float, vnx32sf, 0) \ - T (float, vnx32sf, 3) \ - T (float, vnx32sf, 12) \ - T (float, vnx32sf, 17) \ - T (float, vnx32sf, 14) \ - T (double, vnx16df, 0) \ - T (double, vnx16df, 4) \ - T (double, vnx16df, 8) \ - T (double, vnx16df, 12) \ - T (int64_t, vnx16di, 0) \ - T (int64_t, vnx16di, 4) \ - T (int64_t, vnx16di, 8) \ - T (int64_t, vnx16di, 12) \ - T (int32_t, vnx32si, 0) \ - T (int32_t, vnx32si, 4) \ - T (int32_t, vnx32si, 12) \ - T (int32_t, vnx32si, 16) \ - T (int32_t, vnx32si, 28) \ - T (int16_t, vnx64hi, 0) \ - T (int16_t, vnx64hi, 4) \ - T (int16_t, vnx64hi, 28) \ - T (int16_t, vnx64hi, 32) \ - T (int16_t, vnx64hi, 60) \ - T (int8_t, vnx128qi, 0) \ - T (int8_t, vnx128qi, 4) \ - T (int8_t, vnx128qi, 30) \ - T (int8_t, vnx128qi, 60) \ - T (int8_t, vnx128qi, 64) \ - T (int8_t, vnx128qi, 127) \ - -CHECK_ALL (CHECK) +#define CHECK_VAR(S, V) \ +__attribute__ ((noipa)) \ +void check_var_##V (int32_t idx) \ + { \ + V v; \ + for (int i = 0; i < sizeof (V) / sizeof (S); i++) \ + v[i] = i; \ + S res = vec_extract_var_##V (v, idx); \ + assert (res == v[idx]); \ + } -#define RUN(S, V, IDX) \ +#define RUN(S, V, IDX) \ check_##V##_##IDX (); -#define RUN_ALL(T) \ +#define RUN_VAR(S, V) \ + for (int i = 0; i < sizeof (V) / sizeof (S); i++) \ + check_var_##V (i); \ + +#define RUN_ALL(T) \ T (float, vnx4sf, 0) \ T (float, vnx4sf, 1) \ T (float, vnx4sf, 3) \ @@ -233,7 +141,37 @@ CHECK_ALL (CHECK) T (int8_t, vnx128qi, 64) \ T (int8_t, vnx128qi, 127) \ +#define RUN_ALL_VAR(T) \ + T (float, vnx4sf) \ + T (double, vnx2df) \ + T (int64_t, vnx2di) \ + T (int32_t, vnx4si) \ + T (int16_t, vnx8hi) \ + T (int8_t, vnx16qi) \ + T (float, vnx8sf) \ + T (double, vnx4df) \ + T (int64_t, vnx4di) \ + T (int32_t, vnx8si) \ + T (int16_t, vnx16hi) \ + T (int8_t, vnx32qi) \ + T (float, vnx16sf) \ + T (double, vnx8df) \ + T (int64_t, vnx8di) \ + T (int32_t, vnx16si) \ + T (int16_t, vnx32hi) \ + T (int8_t, vnx64qi) \ + T (float, vnx32sf) \ + T (double, vnx16df) \ + T (int64_t, vnx16di) \ + T (int32_t, vnx32si) \ + T (int16_t, vnx64hi) \ + T (int8_t, vnx128qi) \ + +RUN_ALL (CHECK) +RUN_ALL_VAR (CHECK_VAR) + int main () { RUN_ALL (RUN); + RUN_ALL_VAR (RUN_VAR); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c index db54acc6535..365480ec254 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c @@ -18,35 +18,24 @@ void check_##V##_##IDX () \ assert (res == v[IDX]); \ } -#define CHECK_ALL(T) \ - T (_Float16, vnx8hf, 0) \ - T (_Float16, vnx8hf, 3) \ - T (_Float16, vnx8hf, 7) \ - T (_Float16, vnx16hf, 0) \ - T (_Float16, vnx16hf, 3) \ - T (_Float16, vnx16hf, 7) \ - T (_Float16, vnx16hf, 8) \ - T (_Float16, vnx16hf, 15) \ - T (_Float16, vnx32hf, 0) \ - T (_Float16, vnx32hf, 3) \ - T (_Float16, vnx32hf, 7) \ - T (_Float16, vnx32hf, 8) \ - T (_Float16, vnx32hf, 16) \ - T (_Float16, vnx32hf, 31) \ - T (_Float16, vnx64hf, 0) \ - T (_Float16, vnx64hf, 3) \ - T (_Float16, vnx64hf, 7) \ - T (_Float16, vnx64hf, 8) \ - T (_Float16, vnx64hf, 16) \ - T (_Float16, vnx64hf, 31) \ - T (_Float16, vnx64hf, 42) \ - T (_Float16, vnx64hf, 63) \ - -CHECK_ALL (CHECK) +#define CHECK_VAR(S, V) \ +__attribute__ ((noipa)) \ +void check_var_##V (int32_t idx) \ + { \ + V v; \ + for (int i = 0; i < sizeof (V) / sizeof (S); i++) \ + v[i] = i; \ + S res = vec_extract_var_##V (v, idx); \ + assert (res == v[idx]); \ + } #define RUN(S, V, IDX) \ check_##V##_##IDX (); +#define RUN_VAR(S, V) \ + for (int i = 0; i < sizeof (V) / sizeof (S); i++) \ + check_var_##V (i); \ + #define RUN_ALL(T) \ T (_Float16, vnx8hf, 0) \ T (_Float16, vnx8hf, 3) \ @@ -71,7 +60,17 @@ CHECK_ALL (CHECK) T (_Float16, vnx64hf, 42) \ T (_Float16, vnx64hf, 63) \ +#define RUN_ALL_VAR(T) \ + T (_Float16, vnx8hf) \ + T (_Float16, vnx16hf) \ + T (_Float16, vnx32hf) \ + T (_Float16, vnx64hf) \ + +RUN_ALL (CHECK) +RUN_ALL_VAR (CHECK_VAR) + int main () { RUN_ALL (RUN); + RUN_ALL_VAR (RUN_VAR) }