From patchwork Thu Aug 10 03:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1819679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=TWlfTAAM; dkim-atps=neutral Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLsRX6Vv4z1yYl for ; Thu, 10 Aug 2023 13:12:24 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A6D0B3857718 for ; Thu, 10 Aug 2023 03:12:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6D0B3857718 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691637142; bh=dSSXMDKdim8SQqxlxYKF0l7JrmVHYhIE1JkgHTGLjwg=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=TWlfTAAM1gVhoK/Uy1NbimY7jst7uY2BjLpZkpq1hQ3EIc4ThRckU/nix1luKpAgX zbS+dhiXEYnpvIBeTmbOVL2bjGQWX40OOSQ1jUre/DsucHbhRjQqmvtZd0HE/YzbHj GIIhiM56wspnEjKfI/gPhKjiP13AyfOPAY05syNs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id EAD763858035 for ; Thu, 10 Aug 2023 03:11:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EAD763858035 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 2A636300089; Thu, 10 Aug 2023 03:11:12 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 1/1] RISC-V: Make "prefetch.i" built-in usable Date: Thu, 10 Aug 2023 03:10:57 +0000 Message-ID: <97c0d824fa5aeaee52a825da7f7a17ae8616c5ab.1691636916.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Tsukasa OI The "__builtin_riscv_zicbop_cbo_prefetchi" built-in function was terribly broken so that practically unusable. It emitted "prefetch.i" but with no meaningful arguments. Though incompatible, this commit completely changes the function prototype of this built-in and makes it usable. To minimize the functionality issues, it renames the built-in to "__builtin_riscv_zicbop_prefetch_i". gcc/ChangeLog: * config/riscv/riscv-cmo.def: Fix function prototype. * config/riscv/riscv.md (riscv_prefetchi_): Fix instruction prototype. Remove possible prefectch type argument * doc/extend.texi: Document __builtin_riscv_zicbop_prefetch_i. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbop-1.c: Reflect new built-in prototype. * gcc.target/riscv/cmo-zicbop-2.c: Likewise. --- gcc/config/riscv/riscv-cmo.def | 4 ++-- gcc/config/riscv/riscv.md | 5 ++--- gcc/doc/extend.texi | 7 +++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 10 ++++++---- 5 files changed, 22 insertions(+), 12 deletions(-) diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def index b92044dc6ff9..2286c8a25544 100644 --- a/gcc/config/riscv/riscv-cmo.def +++ b/gcc/config/riscv/riscv-cmo.def @@ -13,8 +13,8 @@ RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero64), // zicbop -RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32), -RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64), +RISCV_BUILTIN (prefetchi_si, "zicbop_prefetch_i", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, prefetchi32), +RISCV_BUILTIN (prefetchi_di, "zicbop_prefetch_i", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, prefetchi64), // zbkc or zbc RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, clmul_zbkc32_or_zbc32), diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 688fd697255b..5658c7b7e113 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3273,9 +3273,8 @@ }) (define_insn "riscv_prefetchi_" - [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") - (match_operand:X 1 "imm5_operand" "i")] - UNSPECV_PREI)] + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] + UNSPECV_PREI)] "TARGET_ZICBOP" "prefetch.i\t%a0" ) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 89c5b4ea2b20..0eb98fc89e3f 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21575,6 +21575,13 @@ Xgnuzihintpausestate extension, which redefines the @code{pause} instruction to change architectural state. @enddefbuiltin +@defbuiltin{void __builtin_riscv_zicbop_prefetch_i (void *@var{addr})} +Generates the @code{prefetch.i} machine instruction to instruct the hardware +that a cache block containing @var{addr} is likely to be accessed by an +instruction fetch in the near future. +Available if the Zicbop extension is enabled. +@enddefbuiltin + @node RISC-V Vector Intrinsics @subsection RISC-V Vector Intrinsics diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c index c5d78c1763d3..0d5b58c4fadf 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -13,11 +13,13 @@ void foo (char *p) __builtin_prefetch (p, 1, 3); } -int foo1() +void foo1 () { - return __builtin_riscv_zicbop_cbo_prefetchi(1); + __builtin_riscv_zicbop_prefetch_i(0); + __builtin_riscv_zicbop_prefetch_i(&foo); + __builtin_riscv_zicbop_prefetch_i((void*)0x111); } -/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.i" 3 } } */ /* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ /* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c index 6576365b39ca..09655c4b8593 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -13,11 +13,13 @@ void foo (char *p) __builtin_prefetch (p, 1, 3); } -int foo1() +void foo1 () { - return __builtin_riscv_zicbop_cbo_prefetchi(1); + __builtin_riscv_zicbop_prefetch_i(0); + __builtin_riscv_zicbop_prefetch_i(&foo); + __builtin_riscv_zicbop_prefetch_i((void*)0x111); } -/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.i" 3 } } */ /* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ -/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */