diff mbox series

testsuite, rs6000: Make {vmx,vsx,p8vector}_hw check for altivec/vsx feature

Message ID 96740202-7882-d0e5-c08b-587dfe491c57@linux.ibm.com
State New
Headers show
Series testsuite, rs6000: Make {vmx,vsx,p8vector}_hw check for altivec/vsx feature | expand

Commit Message

Kewen.Lin July 31, 2024, 9:07 a.m. UTC 
Hi,

Different from p9vector_hw, vmx_hw/vsx_hw/p8vector_hw checks
can still succeed without Altivec/VSX feature support.  We
have many runnable test cases only checking for these *_hw
without extra checking for if Altivec/VSX feature enabled or
not.  It means they can fail if being tested by explicitly
disabling Altivec/VSX.  So I think it's reasonable to check
if Altivec/VSX feature is enabled too while checking testing
environment is able to execute some instructions since these
instructions reply on these features.  So similar to what we
test for p9vector_hw, this patch is to modify C functions
used for vmx_hw, vsx_hw and p8vector_hw with according vector
types and constraints.  For p8vector_hw, excepting for VSX
feature, it also requires ISA 2.7 support.  A good thing is
that now almost all of the test cases using p8vector_hw have
specified -mdejagnu-cpu=power8 always or if !has_arch_pwr8.
Considering checking _ARCH_PWR8 in p8vector_hw can stop test
cases being tested even if test case itself has specified
-mdejagnu-cpu=power8, this patch doesn't force p8vector_hw to
check _ARCH_PWR8, instead it updates all existing test cases
which adopt p8vector_hw but don't have -mdejagnu-cpu=power8.
By the way, all test cases adopting p9vector_hw are all fine.

Bootstrapped and regtested on powerpc64-linux-gnu P8/P9 and
powerpc64le-linux-gnu P9 and P10.

I'm going to push this next week if no objections.

BR,
Kewen
----

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp (check_vsx_hw_available): Modify C source
	code used for testing with type vector long long and constraint wa
	which require VSX feature.
	(check_p8vector_hw_available): Likewise.
	(check_vmx_hw_available): Modify C source code used for testing with
	type vector int and constraint v which require Altivec feature.
	* gcc.target/powerpc/divkc3-1.c: Specify -mdejagnu-cpu=power8 for
	!has_arch_pwr8 to ensure power8 support.
	* gcc.target/powerpc/mulkc3-1.c: Likewise.
	* gcc.target/powerpc/pr96264.c: Likewise.
---
 gcc/testsuite/gcc.target/powerpc/divkc3-1.c |  1 +
 gcc/testsuite/gcc.target/powerpc/mulkc3-1.c |  1 +
 gcc/testsuite/gcc.target/powerpc/pr96264.c  |  1 +
 gcc/testsuite/lib/target-supports.exp       | 24 ++++++++-------------
 4 files changed, 12 insertions(+), 15 deletions(-)

--
2.43.5
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
index 89bf04f12a9..96fb5c21204 100644
--- a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
@@ -1,5 +1,6 @@ 
 /* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */
 /* { dg-options "-mfloat128 -mvsx" } */
+/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */

 void abort ();

diff --git a/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c b/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c
index b975a91dbd7..1b0a1e24814 100644
--- a/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c
@@ -1,5 +1,6 @@ 
 /* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */
 /* { dg-options "-mfloat128 -mvsx" } */
+/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */

 void abort ();

diff --git a/gcc/testsuite/gcc.target/powerpc/pr96264.c b/gcc/testsuite/gcc.target/powerpc/pr96264.c
index 9f7d885daf2..906720fdcd1 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr96264.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr96264.c
@@ -1,5 +1,6 @@ 
 /* { dg-do run { target { powerpc64le-*-* } } } */
 /* { dg-options "-Os -fno-forward-propagate -fschedule-insns -fno-tree-ter -Wno-psabi" } */
+/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */
 /* { dg-require-effective-target p8vector_hw } */

 typedef unsigned char __attribute__ ((__vector_size__ (64))) v512u8;
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index daa0c75d2bc..2101e9c9c83 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2864,11 +2864,9 @@  proc check_p8vector_hw_available { } {
 	    check_runtime_nocache p8vector_hw_available {
 		int main()
 		{
-		#ifdef __MACH__
-		  asm volatile ("xxlorc vs0,vs0,vs0");
-		#else
-		  asm volatile ("xxlorc 0,0,0");
-		#endif
+		  vector long long v1 = {0x1, 0x2};
+		  vector long long v2;
+		  asm ("xxlorc %0,%1,%1" : "=wa" (v2) : "wa" (v1));
 		  return 0;
 		}
 	    } $options
@@ -3165,11 +3163,9 @@  proc check_vsx_hw_available { } {
 	    check_runtime_nocache vsx_hw_available {
 		int main()
 		{
-		#ifdef __MACH__
-		  asm volatile ("xxlor vs0,vs0,vs0");
-		#else
-		  asm volatile ("xxlor 0,0,0");
-		#endif
+		  vector int v1 = {0, 0, 0, 0};
+		  vector int v2;
+		  asm ("xxlor %0,%1,%1" : "=wa" (v2) : "wa" (v1));
 		  return 0;
 		}
 	    } $options
@@ -3198,11 +3194,9 @@  proc check_vmx_hw_available { } {
 	    check_runtime_nocache vmx_hw_available {
 		int main()
 		{
-		#ifdef __MACH__
-		  asm volatile ("vor v0,v0,v0");
-		#else
-		  asm volatile ("vor 0,0,0");
-		#endif
+		  vector int v1 = {0, 0, 0, 0};
+		  vector int v2;
+		  asm ("vor %0,%1,%1" : "=v" (v2) : "v" (v1));
 		  return 0;
 		}
 	    } $options