From patchwork Thu Apr 16 12:27:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1271698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 492z4n1W5Zz9sSG for ; Thu, 16 Apr 2020 22:27:21 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B6868386F00A; Thu, 16 Apr 2020 12:27:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 66B363846047 for ; Thu, 16 Apr 2020 12:27:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 66B363846047 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24BEAC14 for ; Thu, 16 Apr 2020 05:27:15 -0700 (PDT) Received: from [10.57.25.163] (unknown [10.57.25.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D34E93F73D for ; Thu, 16 Apr 2020 05:27:14 -0700 (PDT) From: "Andre Vieira (lists)" Subject: [PATCH 18/19][GCC-8] aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] To: "gcc-patches@gcc.gnu.org" Message-ID: <8a313879-13db-bfb2-48af-181bf9daa29e@arm.com> Date: Thu, 16 Apr 2020 13:27:13 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 Content-Language: en-US X-Spam-Status: No, score=-28.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits invalid RTL. For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits into that mode) and x being SImode; for non-CONST_INT y it zero extends y into SImode and compares that against x, for CONST_INT y it zero extends y into SImode.  The problem is that when the zero extended constant isn't usable directly, it forces it into a REG, but with y_mode mode, and then compares against y.  That is wrong, because it should force it into a SImode REG and compare that way. 2020-04-16  Andre Vieira     Backport from mainline     2020-04-02  Jakub Jelinek     PR target/94435     * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For     y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.     * gcc.target/aarch64/pr94435.c: New test. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 21124b5a3479dd388eb767402e080e2181153467..6bac63402e508027e77a9f4557cb10c578ea7c2c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1556,7 +1556,10 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y, if (y_mode == E_QImode || y_mode == E_HImode) { if (CONST_INT_P (y)) - y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode)); + { + y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode)); + y_mode = SImode; + } else { rtx t, cc_reg; diff --git a/gcc/testsuite/gcc.target/aarch64/pr94435.c b/gcc/testsuite/gcc.target/aarch64/pr94435.c new file mode 100644 index 0000000000000000000000000000000000000000..5713c14d5f90b1d42f92d040e9030ecc03c97d51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr94435.c @@ -0,0 +1,25 @@ +/* PR target/94435 */ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */ + +int b, c, d, e, f, h; +short g; +int foo (int) __attribute__ ((__const__)); + +void +bar (void) +{ + while (1) + { + while (1) + { + __atomic_load_n (&e, 0); + if (foo (2)) + __sync_val_compare_and_swap (&c, 0, f); + b = 1; + if (h == e) + break; + } + __sync_val_compare_and_swap (&g, -1, f); + } +}