From patchwork Tue Jul 28 20:36:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 501469 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E3C5D140D2E for ; Wed, 29 Jul 2015 06:37:09 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=dRHOz1Wj; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=dFW5qIfAhfW+IzPK c0JmaKAloQRQNPjzwp8Ood/7tsM+lp/DBTYuv2jqUhn/t0vWuH4dmuBWBhniG5c1 5Ty8moVSHVFnkI5LekGtCicPtEOoymTsVCTKqMJIEQwq8OCiHX53muPpjqIwLySb uH0j4SZDdkIoqm3FwPZ32SG45WI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=FUZq+4Km45YmKmBoGQTBau 7FCvc=; b=dRHOz1WjgZ6tQBklsRh7SQvHntgSpWNP++ChRKIcxCEbYzZYY/LH+V dmxQSFidnPgBfyfwlofUybDURUXz5mYuyX2HSz3G0YPgmgV8ZtESKJWYcsoOFew9 2mHb2bKUfv/g/p5P4SezySsuyP+nhMP4lROWM1av4nGzHvmzIv2HU= Received: (qmail 129709 invoked by alias); 28 Jul 2015 20:37:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 129699 invoked by uid 89); 28 Jul 2015 20:37:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.0 required=5.0 tests=AWL, BAYES_40, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 28 Jul 2015 20:37:02 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-2-x-0XtiJpTmSx_GCVNgajLw-1; Tue, 28 Jul 2015 21:36:57 +0100 Received: from localhost ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 28 Jul 2015 21:36:57 +0100 From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] Use target-insns.def for atomic_test_and_set Date: Tue, 28 Jul 2015 21:36:57 +0100 Message-ID: <87r3nsm32u.fsf@e105548-lin.cambridge.arm.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 X-MC-Unique: x-0XtiJpTmSx_GCVNgajLw-1 Bootstrapped & regression-tested on x86_64-linux-gnu and aarch64-linux-gnu. Also tested via config-list.mk. Committed as preapproved. Thanks, Richard gcc/ * target-insns.def (atomic_test_and_set): New targetm instruction pattern. * optabs.c (maybe_emit_atomic_test_and_set): Use it instead of HAVE_*/gen_* interface. Index: gcc/target-insns.def =================================================================== --- gcc/target-insns.def 2015-07-28 21:00:09.815019853 +0100 +++ gcc/target-insns.def 2015-07-28 21:00:09.811019905 +0100 @@ -31,6 +31,7 @@ Instructions should be documented in md.texi rather than here. */ DEF_TARGET_INSN (allocate_stack, (rtx x0, rtx x1)) +DEF_TARGET_INSN (atomic_test_and_set, (rtx x0, rtx x1, rtx x2)) DEF_TARGET_INSN (builtin_longjmp, (rtx x0)) DEF_TARGET_INSN (builtin_setjmp_receiver, (rtx x0)) DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0)) Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2015-07-28 21:00:09.815019853 +0100 +++ gcc/optabs.c 2015-07-28 21:00:09.811019905 +0100 @@ -7258,35 +7258,30 @@ maybe_emit_compare_and_swap_exchange_loo using the atomic_test_and_set instruction pattern. A boolean value is returned from the operation, using TARGET if possible. */ -#ifndef HAVE_atomic_test_and_set -#define HAVE_atomic_test_and_set 0 -#define CODE_FOR_atomic_test_and_set CODE_FOR_nothing -#endif - static rtx maybe_emit_atomic_test_and_set (rtx target, rtx mem, enum memmodel model) { machine_mode pat_bool_mode; struct expand_operand ops[3]; - if (!HAVE_atomic_test_and_set) + if (!targetm.have_atomic_test_and_set ()) return NULL_RTX; /* While we always get QImode from __atomic_test_and_set, we get other memory modes from __sync_lock_test_and_set. Note that we use no endian adjustment here. This matches the 4.6 behavior in the Sparc backend. */ - gcc_checking_assert - (insn_data[CODE_FOR_atomic_test_and_set].operand[1].mode == QImode); + enum insn_code icode = targetm.code_for_atomic_test_and_set; + gcc_checking_assert (insn_data[icode].operand[1].mode == QImode); if (GET_MODE (mem) != QImode) mem = adjust_address_nv (mem, QImode, 0); - pat_bool_mode = insn_data[CODE_FOR_atomic_test_and_set].operand[0].mode; + pat_bool_mode = insn_data[icode].operand[0].mode; create_output_operand (&ops[0], target, pat_bool_mode); create_fixed_operand (&ops[1], mem); create_integer_operand (&ops[2], model); - if (maybe_expand_insn (CODE_FOR_atomic_test_and_set, 3, ops)) + if (maybe_expand_insn (icode, 3, ops)) return ops[0].value; return NULL_RTX; }