From patchwork Tue Apr 14 16:53:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 461202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8BFA11400DE for ; Wed, 15 Apr 2015 02:54:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=MyFMwCrs; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=CtRq7jtLtzJMnbsQgz3yTfS4132lgt0RIGvylloDyjT11OKxq6 3hBxMTn1Z8gMBi5UnSDlXbwfjs8jYrLH/Bqh4386EE8vxzNiTxgqE5HrhBpCikHT xGIhRKmeEZ6MVzRVKzHjoKqjeYczty67SN6fiWf/iT/LmkpujMzw+zReE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=J9Tmi6aqqmX2H1D347Pq/G+738U=; b=MyFMwCrsPREcpbbEOvOr C015X3QGLycLYY+sAr+K2wxLY8FrZpHCIIbaFIdxqZE6xdRbndTmjKXHD5MoIo9e JG9Ha8jkVhD4eEUoLejlKAQdz5Ycow7B++xIucOznno7oVppORRxXDIsMWFhC/4o P5/gqIPdBX8HeDxvR7MmWLA= Received: (qmail 108180 invoked by alias); 14 Apr 2015 16:53:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 108144 invoked by uid 89); 14 Apr 2015 16:53:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, KAM_STOCKGEN, SPF_HELO_PASS, SPF_PASS, SUBJ_ALL_CAPS, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 14 Apr 2015 16:53:48 +0000 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id 090C28E6E9 for ; Tue, 14 Apr 2015 16:53:46 +0000 (UTC) Received: from littlehelper.redhat.com (vpn1-4-135.ams2.redhat.com [10.36.4.135]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t3EGriRJ017890 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 14 Apr 2015 12:53:45 -0400 From: Nick Clifton To: dj@redhat.com Cc: gcc-patches@gcc.gnu.org Subject: RFA: RL78: Date: Tue, 14 Apr 2015 17:53:43 +0100 Message-ID: <87pp76odm0.fsf@redhat.com> MIME-Version: 1.0 X-IsSubscribed: yes Hi DJ, I would like permission to apply this patch to the RL78 backend. It tidies up a few minor bugs, specifically: * The prologue instruction to increment the stack pointer by a large amount was not being marked as frame related. * The %p operand operator was not using %code when applied to a function symbol. * Reload could in very rare circumstances fail to compute a suitable register class. * The expanders in rl78.md contain constraints that are not used. * The multiply insns in rl78.md mark operand 1 as both input and output when in fact it is only an input. Tested with no regressions on an rl78-elf toolchain. OK to apply ? Cheers Nick 2015-04-14 Nick Clifton * config/rl78/rl78.c (rl78_expand_prologue): Mark large stack decrement instruction as being frame related. (rl78_print_operand_1): Handle 'p' modifier to add +0 to HL based addresses. If zero extending a function address enclose the operation in %code(...). (rl78_preferred_reload_class): New function. (TARGET_PREFERRED_RELOAD_CLASS): Define. * config/rl78/rl78.md: Remove useless constraints in expanders. (mulqi3_rl78): Remove + qualifier on input-only operand 1. (mulhi3_rl78): Likewise. (mulhi3_g13): Likewise. (mulsi3_rl78): Likewise. (es_addr): Move to before the multiply patterns. Index: config/rl78/rl78.c =================================================================== --- config/rl78/rl78.c (revision 222096) +++ config/rl78/rl78.c (working copy) @@ -1322,7 +1322,7 @@ emit_move_insn (ax, sp); emit_insn (gen_subhi3 (ax, ax, GEN_INT (fs))); - insn = emit_move_insn (sp, ax); + insn = F (emit_move_insn (sp, ax)); add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_SET (SImode, sp, gen_rtx_PLUS (HImode, sp, GEN_INT (-fs)))); @@ -1570,6 +1570,7 @@ e - third QI of an SI (i.e. where the ES register gets values from) E - fourth QI of an SI (i.e. MSB) + p - Add +0 to a zero-indexed HL based address. */ /* Implements the bulk of rl78_print_operand, below. We do it this @@ -1644,13 +1645,16 @@ rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 1), 'u'); fprintf (file, "["); rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 0), 0); + if (letter == 'p' && GET_CODE (XEXP (op, 0)) == REG) + fprintf (file, "+0"); fprintf (file, "]"); } else { + op = XEXP (op, 0); fprintf (file, "["); - rl78_print_operand_1 (file, XEXP (op, 0), letter); - if (letter == 'p' && GET_CODE (XEXP (op, 0)) == REG) + rl78_print_operand_1 (file, op, letter); + if (letter == 'p' && REG_P (op) && REGNO (op) == 6) fprintf (file, "+0"); fprintf (file, "]"); } @@ -1772,15 +1776,41 @@ if (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND) { - rl78_print_operand_1 (file, XEXP (op, 1), letter); - fprintf (file, "+"); - rl78_print_operand_1 (file, XEXP (op, 0), letter); + if (GET_CODE (XEXP (op, 1)) == SYMBOL_REF + && SYMBOL_REF_DECL (XEXP (op, 1)) + && TREE_CODE (SYMBOL_REF_DECL (XEXP (op, 1))) == FUNCTION_DECL) + { + fprintf (file, "%%code("); + assemble_name (file, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op, 1), 0))); + fprintf (file, "+"); + rl78_print_operand_1 (file, XEXP (op, 0), letter); + fprintf (file, ")"); + } + else + { + rl78_print_operand_1 (file, XEXP (op, 1), letter); + fprintf (file, "+"); + rl78_print_operand_1 (file, XEXP (op, 0), letter); + } } else { - rl78_print_operand_1 (file, XEXP (op, 0), letter); - fprintf (file, "+"); - rl78_print_operand_1 (file, XEXP (op, 1), letter); + if (GET_CODE (XEXP (op, 0)) == SYMBOL_REF + && SYMBOL_REF_DECL (XEXP (op, 0)) + && TREE_CODE (SYMBOL_REF_DECL (XEXP (op, 0))) == FUNCTION_DECL) + { + fprintf (file, "%%code("); + assemble_name (file, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op, 0), 0))); + fprintf (file, "+"); + rl78_print_operand_1 (file, XEXP (op, 1), letter); + fprintf (file, ")"); + } + else + { + rl78_print_operand_1 (file, XEXP (op, 0), letter); + fprintf (file, "+"); + rl78_print_operand_1 (file, XEXP (op, 1), letter); + } } if (need_paren) fprintf (file, ")"); @@ -4509,6 +4544,19 @@ return res; } +#undef TARGET_PREFERRED_RELOAD_CLASS +#define TARGET_PREFERRED_RELOAD_CLASS rl78_preferred_reload_class + +static reg_class_t +rl78_preferred_reload_class (rtx x, reg_class_t rclass) +{ + if (rclass == NO_REGS) + rclass = V_REGS; + + return rclass; +} + + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rl78.h" Index: config/rl78/rl78.md =================================================================== --- config/rl78/rl78.md (revision 222096) +++ config/rl78/rl78.md (working copy) @@ -107,7 +107,7 @@ ) (define_expand "eh_return" - [(match_operand:HI 0 "" "")] + [(match_operand:HI 0 "")] "" "rl78_expand_eh_epilogue (operands[0]); emit_barrier (); @@ -169,10 +169,10 @@ ;; non-immediate as well. (define_expand "nonlocal_goto" [(set (pc) - (unspec_volatile [(match_operand 0 "" "") ;; fp (ignore) - (match_operand 1 "" "vi") ;; target - (match_operand 2 "" "vi") ;; sp - (match_operand 3 "" "vi") ;; ? + (unspec_volatile [(match_operand 0 "") ;; fp (ignore) + (match_operand 1 "") ;; target + (match_operand 2 "") ;; sp + (match_operand 3 "") ;; ? ] UNS_NONLOCAL_GOTO)) ] "" @@ -200,6 +200,14 @@ " ) +(define_expand "es_addr" + [(unspec:SI [(reg:QI ES_REG) + (match_operand:HI 0 "") + ] UNS_ES_ADDR)] + "" + "" +) + ;;====================================================================== ;; ;; "macro" insns - cases where inline chunks of code are more @@ -243,9 +251,9 @@ ) (define_expand "subsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "=&vm") - (minus:SI (match_operand:SI 1 "general_operand" "vim") - (match_operand 2 "general_operand" "vim"))) + [(set (match_operand:SI 0 "nonimmediate_operand") + (minus:SI (match_operand:SI 1 "general_operand") + (match_operand 2 "general_operand"))) ] "" "emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2])); @@ -280,9 +288,9 @@ ) (define_expand "mulqi3" - [(set (match_operand:QI 0 "register_operand" "") - (mult:QI (match_operand:QI 1 "general_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + [(set (match_operand:QI 0 "register_operand") + (mult:QI (match_operand:QI 1 "general_operand") + (match_operand:QI 2 "nonmemory_operand"))) ] "" ; mulu supported by all targets "" @@ -289,9 +297,9 @@ ) (define_expand "mulhi3" - [(set (match_operand:HI 0 "register_operand" "") - (mult:HI (match_operand:HI 1 "general_operand" "") - (match_operand:HI 2 "nonmemory_operand" ""))) + [(set (match_operand:HI 0 "register_operand") + (mult:HI (match_operand:HI 1 "general_operand") + (match_operand:HI 2 "nonmemory_operand"))) ] "! RL78_MUL_NONE" "" @@ -298,8 +306,8 @@ ) (define_expand "mulsi3" - [(set (match_operand:SI 0 "register_operand" "=&v") - (mult:SI (match_operand:SI 1 "general_operand" "+vim") + [(set (match_operand:SI 0 "register_operand" "=&v") + (mult:SI (match_operand:SI 1 "general_operand" "vim") (match_operand:SI 2 "nonmemory_operand" "vi"))) ] "! RL78_MUL_NONE" @@ -308,7 +316,7 @@ (define_insn "*mulqi3_rl78" [(set (match_operand:QI 0 "register_operand" "=&v") - (mult:QI (match_operand:QI 1 "general_operand" "+viU") + (mult:QI (match_operand:QI 1 "general_operand" "viU") (match_operand:QI 2 "general_operand" "vi"))) ] "" ; mulu supported by all targets @@ -325,7 +333,7 @@ (define_insn "*mulhi3_rl78" [(set (match_operand:HI 0 "register_operand" "=&v") - (mult:HI (match_operand:HI 1 "general_operand" "+viU") + (mult:HI (match_operand:HI 1 "general_operand" "viU") (match_operand:HI 2 "general_operand" "vi"))) ] "RL78_MUL_RL78" @@ -340,7 +348,7 @@ (define_insn "*mulhi3_g13" [(set (match_operand:HI 0 "register_operand" "=&v") - (mult:HI (match_operand:HI 1 "general_operand" "+viU") + (mult:HI (match_operand:HI 1 "general_operand" "viU") (match_operand:HI 2 "general_operand" "vi"))) ] "RL78_MUL_G13" @@ -363,7 +371,7 @@ ;; bits of the result). (define_insn "mulsi3_rl78" [(set (match_operand:SI 0 "register_operand" "=&v") - (mult:SI (match_operand:SI 1 "general_operand" "+viU") + (mult:SI (match_operand:SI 1 "general_operand" "viU") (match_operand:SI 2 "general_operand" "vi"))) ] "RL78_MUL_RL78" @@ -432,12 +440,4 @@ movw %H0, ax ; end of mulsi macro" [(set_attr "valloc" "macax")] - ) - -(define_expand "es_addr" - [(unspec:SI [(reg:QI ES_REG) - (match_operand:HI 0 "" "") - ] UNS_ES_ADDR)] - "" - "" )