From patchwork Tue Jun 30 20:56:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 489812 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E52BE1402A1 for ; Wed, 1 Jul 2015 06:56:58 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=lOo5oD+f; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=OYEO/yLgULfBSTnO X0WdsxoCz2wq/9NWs01t92qF+jWjFay71r0Py1+0P1lMHMQceepQSEKziH7V6wvX JqIRD2OH19AdlX1K4rivnvEgbr2kKhyCeB8ji34ArPBHaRrKAhm9Am2hhrNVjTUB 52gPKEOZi+BW6XkXuaXSe4fLtTA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=7juYVwZyRCSff9vgpsEWsO 6UIzM=; b=lOo5oD+fxDp+wJOdDN7QGXXR29uvf4OP5QgfJiKPrq0WKwhV+J62o3 HAuscrUZPnqcpIIf5DZmk7lH7ZWH5DA93l+S5kGGeJIqH8q4af6x/BvT/S5DpOf+ DECurDMMFS5VW7OEzaOlEf2JwO6GO6Fuz5LqXJAsJdTPem7rnzvDw= Received: (qmail 73791 invoked by alias); 30 Jun 2015 20:56:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73782 invoked by uid 89); 30 Jun 2015 20:56:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL, BAYES_50, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 30 Jun 2015 20:56:49 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-2-JOQBK01vTIepr1Z4S9kvdg-1 Received: from localhost ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 30 Jun 2015 21:56:44 +0100 From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] Use target-insns.def for {load,store}_multiple Date: Tue, 30 Jun 2015 21:56:44 +0100 Message-ID: <87oajwoqyb.fsf@e105548-lin.cambridge.arm.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 X-MC-Unique: JOQBK01vTIepr1Z4S9kvdg-1 Bootstrapped & regression-tested on x86_64-linux-gnu and aarch64-linux-gnu. Also tested via config-list.mk. Committed as preapproved. Thanks, Richard gcc/ * defaults.h (HAVE_load_multiple, gen_load_multiple) (HAVE_store_multiple, gen_store_multiple): Delete. * target-insns.def (load_multiple, store_multiple): New targetm instruction patterns. * expr.c (move_block_to_reg, move_block_from_reg): Use them instead of HAVE_*/gen_* interface. Index: gcc/defaults.h =================================================================== --- gcc/defaults.h 2015-06-30 21:56:16.107263462 +0100 +++ gcc/defaults.h 2015-06-30 21:56:16.083263735 +0100 @@ -1426,26 +1426,6 @@ #define STACK_CHECK_MAX_VAR_SIZE (STACK_ #define TARGET_VTABLE_USES_DESCRIPTORS 0 #endif -#ifndef HAVE_load_multiple -#define HAVE_load_multiple 0 -static inline rtx -gen_load_multiple (rtx, rtx, rtx) -{ - gcc_unreachable (); - return NULL; -} -#endif - -#ifndef HAVE_store_multiple -#define HAVE_store_multiple 0 -static inline rtx -gen_store_multiple (rtx, rtx, rtx) -{ - gcc_unreachable (); - return NULL; -} -#endif - #ifndef HAVE_tablejump #define HAVE_tablejump 0 static inline rtx Index: gcc/target-insns.def =================================================================== --- gcc/target-insns.def 2015-06-30 21:56:16.107263462 +0100 +++ gcc/target-insns.def 2015-06-30 21:56:16.083263735 +0100 @@ -32,6 +32,7 @@ Instructions should be documented in md.texi rather than here. */ DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1)) DEF_TARGET_INSN (epilogue, (void)) +DEF_TARGET_INSN (load_multiple, (rtx x0, rtx x1, rtx x2)) DEF_TARGET_INSN (mem_signal_fence, (rtx x0)) DEF_TARGET_INSN (mem_thread_fence, (rtx x0)) DEF_TARGET_INSN (memory_barrier, (void)) @@ -39,3 +40,4 @@ DEF_TARGET_INSN (prologue, (void)) DEF_TARGET_INSN (return, (void)) DEF_TARGET_INSN (sibcall_epilogue, (void)) DEF_TARGET_INSN (simple_return, (void)) +DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2)) Index: gcc/expr.c =================================================================== --- gcc/expr.c 2015-06-30 21:56:16.107263462 +0100 +++ gcc/expr.c 2015-06-30 21:56:16.083263735 +0100 @@ -1491,10 +1491,6 @@ emit_block_move_via_loop (rtx x, rtx y, void move_block_to_reg (int regno, rtx x, int nregs, machine_mode mode) { - int i; - rtx pat; - rtx_insn *last; - if (nregs == 0) return; @@ -1502,12 +1498,12 @@ move_block_to_reg (int regno, rtx x, int x = validize_mem (force_const_mem (mode, x)); /* See if the machine can do this with a load multiple insn. */ - if (HAVE_load_multiple) + if (targetm.have_load_multiple ()) { - last = get_last_insn (); - pat = gen_load_multiple (gen_rtx_REG (word_mode, regno), x, - GEN_INT (nregs)); - if (pat) + rtx_insn *last = get_last_insn (); + rtx first = gen_rtx_REG (word_mode, regno); + if (rtx_insn *pat = targetm.gen_load_multiple (first, x, + GEN_INT (nregs))) { emit_insn (pat); return; @@ -1516,7 +1512,7 @@ move_block_to_reg (int regno, rtx x, int delete_insns_since (last); } - for (i = 0; i < nregs; i++) + for (int i = 0; i < nregs; i++) emit_move_insn (gen_rtx_REG (word_mode, regno + i), operand_subword_force (x, i, mode)); } @@ -1527,18 +1523,16 @@ move_block_to_reg (int regno, rtx x, int void move_block_from_reg (int regno, rtx x, int nregs) { - int i; - if (nregs == 0) return; /* See if the machine can do this with a store multiple insn. */ - if (HAVE_store_multiple) + if (targetm.have_store_multiple ()) { rtx_insn *last = get_last_insn (); - rtx pat = gen_store_multiple (x, gen_rtx_REG (word_mode, regno), - GEN_INT (nregs)); - if (pat) + rtx first = gen_rtx_REG (word_mode, regno); + if (rtx_insn *pat = targetm.gen_store_multiple (x, first, + GEN_INT (nregs))) { emit_insn (pat); return; @@ -1547,7 +1541,7 @@ move_block_from_reg (int regno, rtx x, i delete_insns_since (last); } - for (i = 0; i < nregs; i++) + for (int i = 0; i < nregs; i++) { rtx tem = operand_subword (x, i, 1, BLKmode);