From patchwork Wed May 13 21:28:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Schwinge X-Patchwork-Id: 472092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DBE8B140758 for ; Thu, 14 May 2015 07:29:19 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=VRzSlisn; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:in-reply-to:references:date:message-id :mime-version:content-type; q=dns; s=default; b=H2laYy1pipTsgH58 XxsXaz9fBYDsyiPdO8GpqHKAJomfoWRId9WzTGrmO0o9gmo7GwjT25AP82xOsLxt bNLN21URNtgaGpDVAi2THn0d0A7EAy8MOfGNKIPFdD4i0jDhdDTnVsEkmVDM0oOi ZPQbKhaq/ZHQzjKDz+a3vbAa5N8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:in-reply-to:references:date:message-id :mime-version:content-type; s=default; bh=WmWiShhJ9iEuAV8tdg+Tlx I8hbI=; b=VRzSlisnPWhOcn2l4h3cXxa5sNSuJ3XdstzUPUB3kqdsXf+0Ov3KKl M7NPeIgy+on0ZHVlzKmHiRp+Y6dB/NeNkakCvyqJRwPjJS2Pap4IlBbQBU4LId56 DhnMH+DV7iFkhXFOR6XUAZqAtr90ywP7mj8l4iZbBZPRfPkBdodts= Received: (qmail 95452 invoked by alias); 13 May 2015 21:29:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 95434 invoked by uid 89); 13 May 2015 21:29:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-Spam-User: qpsmtpd, 2 recipients X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 13 May 2015 21:29:08 +0000 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-01.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1YseD7-0002yB-TP from Thomas_Schwinge@mentor.com ; Wed, 13 May 2015 14:29:02 -0700 Received: from feldtkeller.schwinge.homeip.net (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.3.224.2; Wed, 13 May 2015 22:29:00 +0100 From: Thomas Schwinge To: Satoshi_OHSHIMA , CC: Jakub Jelinek , , Bernd Schmidt Subject: [gomp4] Basic -misa support for nvptx (was: How to use old GPU (Fermi) in gcc with OpenACC?) In-Reply-To: <1431192382076-1147463.post@n5.nabble.com> References: <1431192382076-1147463.post@n5.nabble.com> <552FC777.3040002@codesourcery.com> User-Agent: Notmuch/0.9-101-g81dad07 (http://notmuchmail.org) Emacs/24.3.1 (x86_64-pc-linux-gnu) Date: Wed, 13 May 2015 23:28:42 +0200 Message-ID: <87lhgsjhf9.fsf@schwinge.name> MIME-Version: 1.0 Hi! On Sat, 9 May 2015 10:26:22 -0700, Satoshi_OHSHIMA wrote: > I'm trying to use and evaluate gcc with OpenACC on some NVIDIA GPUs. > I succeeded to build gcc with OpenACC by using > http://scelementary.com/2015/04/25/openacc-in-gcc.html as a reference. Heh, their build instructions very much look like the ones I provided in : trunk-offload-big.tar.bz2, trunk-offload-light.tar.bz2 (no problem with them reusing these, of course). > Then, I succeeded to use Kepler GPU. :-) > However, I tried to use it on old GPUs (Fermi), and I failed to execute it. > I noticed that there are some "sm_30" and "COMPUTE_30" keywords in gcc and > nvptx sources. > Then, I modified them to "sm_20" and "COMPUTE_20", but I failed to execute > my programs, too. > Are there any developers who can make gcc with OpenACC to support other than > "sm_30"? "Can", yes, but this is unlikely to happen: a nontrivial amount of work would be required to get the current code (and, in particular, our patches under development) working on what nowadays is probably considered "legacy" hardware. (For example, if I remember correctly, didn't Nvidia remove support for Fermi-class hardware from recent CUDA toolkit releases?) However, I committed the following patch to gomp-4_0-branch in r223182, and you're of course very welcome to follow that route, and contribute patches to properly conditionalize the respective PTX instructions, provide replacement functions, and so on, in gcc/config/nvptx/nvptx.md, libgcc/config/nvptx/, and probably other locations. To use this patch, you'll also need to update your nvptx-tools sources. commit 29001da9572e094164e1fca440925fafbceb67f2 Author: tschwinge Date: Wed May 13 21:25:42 2015 +0000 Basic -misa support for nvptx gcc/ * config/nvptx/nvptx-opts.h: New file. * config/nvptx/nvptx.c (nvptx_file_start): Print the correct .target. * config/nvptx/nvptx.h: Include "nvptx-opts.h". (ASM_SPEC): Define. (TARGET_SM35): New macro. * config/nvptx/nvptx.md (atomic_fetch_): Enable with the correct predicate. * config/nvptx/nvptx.opt (ptx_isa, sm_30, sm_35): New enum and its values. (misa=): New option. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gomp-4_0-branch@223182 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog.gomp | 13 +++++++++++++ gcc/config/nvptx/nvptx-opts.h | 31 +++++++++++++++++++++++++++++++ gcc/config/nvptx/nvptx.c | 5 ++++- gcc/config/nvptx/nvptx.h | 8 ++++++++ gcc/config/nvptx/nvptx.md | 3 +-- gcc/config/nvptx/nvptx.opt | 14 ++++++++++++++ 6 files changed, 71 insertions(+), 3 deletions(-) Grüße, Thomas diff --git gcc/ChangeLog.gomp gcc/ChangeLog.gomp index a4683c3..f43f668 100644 --- gcc/ChangeLog.gomp +++ gcc/ChangeLog.gomp @@ -1,3 +1,16 @@ +2015-05-13 Bernd Schmidt + + * config/nvptx/nvptx-opts.h: New file. + * config/nvptx/nvptx.c (nvptx_file_start): Print the correct .target. + * config/nvptx/nvptx.h: Include "nvptx-opts.h". + (ASM_SPEC): Define. + (TARGET_SM35): New macro. + * config/nvptx/nvptx.md (atomic_fetch_): Enable with the + correct predicate. + * config/nvptx/nvptx.opt (ptx_isa, sm_30, sm_35): New enum and its + values. + (misa=): New option. + 2015-05-13 Cesar Philippidis * except.c (finish_eh_generation): Don't finalize exeception diff --git gcc/config/nvptx/nvptx-opts.h gcc/config/nvptx/nvptx-opts.h new file mode 100644 index 0000000..512c37a --- /dev/null +++ gcc/config/nvptx/nvptx-opts.h @@ -0,0 +1,31 @@ +/* Definitions for the NVPTX port needed for option handling. + Copyright (C) 2015 Free Software Foundation, Inc. + Contributed by Bernd Schmidt + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef NVPTX_OPTS_H +#define NVPTX_OPTS_H + +enum ptx_isa +{ + PTX_ISA_SM30, + PTX_ISA_SM35 +}; + +#endif + diff --git gcc/config/nvptx/nvptx.c gcc/config/nvptx/nvptx.c index 10ac976..9bec12f 100644 --- gcc/config/nvptx/nvptx.c +++ gcc/config/nvptx/nvptx.c @@ -2048,7 +2048,10 @@ nvptx_file_start (void) { fputs ("// BEGIN PREAMBLE\n", asm_out_file); fputs ("\t.version\t3.1\n", asm_out_file); - fputs ("\t.target\tsm_30\n", asm_out_file); + if (TARGET_SM35) + fputs ("\t.target\tsm_35\n", asm_out_file); + else + fputs ("\t.target\tsm_30\n", asm_out_file); fprintf (asm_out_file, "\t.address_size %d\n", GET_MODE_BITSIZE (Pmode)); fprintf (asm_out_file, "\t.extern .shared .u8 sdata[];\n"); fputs ("// END PREAMBLE\n", asm_out_file); diff --git gcc/config/nvptx/nvptx.h gcc/config/nvptx/nvptx.h index e4e58dd..c304121 100644 --- gcc/config/nvptx/nvptx.h +++ gcc/config/nvptx/nvptx.h @@ -21,10 +21,16 @@ #ifndef GCC_NVPTX_H #define GCC_NVPTX_H +#ifndef NVPTX_OPTS_H +#include "config/nvptx/nvptx-opts.h" +#endif + /* Run-time Target. */ #define STARTFILE_SPEC "%{mmainkernel:crt0.o}" +#define ASM_SPEC "%{misa=*:-m %*}" + #define TARGET_CPU_CPP_BUILTINS() \ do \ { \ @@ -77,6 +83,8 @@ #define Pmode (TARGET_ABI64 ? DImode : SImode) +#define TARGET_SM35 (ptx_isa_option >= PTX_ISA_SM35) + /* Registers. Since ptx is a virtual target, we just define a few hard registers for special purposes and leave pseudos unallocated. */ diff --git gcc/config/nvptx/nvptx.md gcc/config/nvptx/nvptx.md index 48f9acf..f5b1a20 100644 --- gcc/config/nvptx/nvptx.md +++ gcc/config/nvptx/nvptx.md @@ -1414,7 +1414,6 @@ (define_code_iterator any_logic [and ior xor]) (define_code_attr logic [(and "and") (ior "or") (xor "xor")]) -;; Currently disabled until we add better subtarget support - requires sm_32. (define_insn "atomic_fetch_" [(set (match_operand:SDIM 1 "memory_operand" "+m") (unspec_volatile:SDIM @@ -1424,5 +1423,5 @@ UNSPECV_LOCK)) (set (match_operand:SDIM 0 "nvptx_register_operand" "=R") (match_dup 1))] - "0" + "mode == SImode || TARGET_SM35" "%.\\tatom%A1.b%T0.\\t%0, %1, %2;") diff --git gcc/config/nvptx/nvptx.opt gcc/config/nvptx/nvptx.opt index 249a61d..9ba050e 100644 --- gcc/config/nvptx/nvptx.opt +++ gcc/config/nvptx/nvptx.opt @@ -28,3 +28,17 @@ Generate code for a 64-bit ABI mmainkernel Target Report RejectNegative Link in code for a __main kernel. + +Enum +Name(ptx_isa) Type(int) +Known PTX ISA versions (for use with the -misa= option): + +EnumValue +Enum(ptx_isa) String(sm_30) Value(PTX_ISA_SM30) + +EnumValue +Enum(ptx_isa) String(sm_35) Value(PTX_ISA_SM35) + +misa= +Target RejectNegative ToLower Joined Enum(ptx_isa) Var(ptx_isa_option) Init(PTX_ISA_SM30) +Specify the version of the ptx ISA to use