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[86.138.95.213]) by smtp.gmail.com with ESMTPSA id g127sm4949522wmf.24.2015.12.15.16.15.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Dec 2015 16:15:32 -0800 (PST) From: Andrew Burgess To: gcc-patches@gcc.gnu.org Cc: Claudiu.Zissulescu@synopsys.com, gnu@amylaar.uk, Andrew Burgess Subject: [PATCH 3/4] gcc/arc: Remove store_update_operand predicate Date: Wed, 16 Dec 2015 00:15:22 +0000 Message-Id: <816068b13fbcb71848031a000a2da51aab2853c0.1450224136.git.andrew.burgess@embecosm.com> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes The use of the arc specific predicate store_update_operand is broken, this commit fixes the error, and in the process removes the need for store_update_operand altogether. Currently store_update_operand is used with match_operator, the store_update_operand checks that the operand is a MEM operand, with an operand that is a plus, the plus in turn has operands that are a register and an immediate. However, the match_operator already checks the structure of the rtl tree, only in this case a different rtl pattern is checked for, in this case the operand must have two child operands, one a register operand and one an immediate operand. The mistake here is that the plus part of the rtl tree has been missed from the define_insn rtl pattern. The consequence of this mistake is that a MEM operand will match the store_update_operand predicate, then the second operand of the MEM insn will then be passed to the nonmemory_operand predicate, which assumes it will be passed an rtl_insn. However, the second operand of a MEM insn is the alias set for the address, not an rtl_insn. When fixing the rtl pattern within the define_insn it becomes obvious that all of the checks currently contained within the store_update_operand predicate are now contains within the rtl pattern, if the use of store_update_operand is replaced with the memory_operand predicate. As with the previous patch in this series, once this patch is applied I see almost all of these instructions being used in the wider GCC testsuite. As with the previous patch, if anyone knows a good way to trigger the generation of specific instructions, tha would be great. gcc/ChangeLog: * config/arc/arc.md (*storeqi_update): Use 'memory_operand' and fix RTL pattern to include the plus. (*storehi_update): Likewise. (*storesi_update): Likewise. (*storesf_update): Likewise. * config/arc/predicates.md (store_update_operand): Delete. --- gcc/ChangeLog | 9 +++++++++ gcc/config/arc/arc.md | 24 ++++++++++++------------ gcc/config/arc/predicates.md | 18 ------------------ 3 files changed, 21 insertions(+), 30 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 705d4e9..dcc0930 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2015-12-09 Andrew Burgess + * config/arc/arc.md (*storeqi_update): Use 'memory_operand' and + fix RTL pattern to include the plus. + (*storehi_update): Likewise. + (*storesi_update): Likewise. + (*storesf_update): Likewise. + * config/arc/predicates.md (store_update_operand): Delete. + +2015-12-09 Andrew Burgess + * config/arc/arc.md (*loadqi_update): Use 'memory_operand' and fix RTL pattern to include the plus. (*load_zeroextendqisi_update): Likewise. diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ef82007..2ca4d1d 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1149,9 +1149,9 @@ (set_attr "length" "4,8")]) (define_insn "*storeqi_update" - [(set (match_operator:QI 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:QI 4 "memory_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:QI 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -1200,9 +1200,9 @@ (set_attr "length" "4,8")]) (define_insn "*storehi_update" - [(set (match_operator:HI 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:HI 4 "memory_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:HI 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -1225,9 +1225,9 @@ (set_attr "length" "4,8")]) (define_insn "*storesi_update" - [(set (match_operator:SI 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:SI 4 "memory_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:SI 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -1249,9 +1249,9 @@ (set_attr "length" "4,8")]) (define_insn "*storesf_update" - [(set (match_operator:SF 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:SF 4 "memory_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:SF 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index bdad135..bb488d1 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -460,24 +460,6 @@ } ) -;; Return true if OP is valid store with update operand. -(define_predicate "store_update_operand" - (match_code "mem") -{ - if (GET_CODE (op) != MEM - || GET_MODE (op) != mode) - return 0; - op = XEXP (op, 0); - if (GET_CODE (op) != PLUS - || GET_MODE (op) != Pmode - || !register_operand (XEXP (op, 0), Pmode) - || !(GET_CODE (XEXP (op, 1)) == CONST_INT - && SMALL_INT (INTVAL (XEXP (op, 1))))) - return 0; - return 1; -} -) - ;; Return true if OP is a non-volatile non-immediate operand. ;; Volatile memory refs require a special "cache-bypass" instruction ;; and only the standard movXX patterns are set up to handle them.