@@ -23,13 +23,32 @@
""
"#"
"&& reload_completed"
- [(set (reg:H8cc CC_REG)
- (compare:H8cc (match_dup 1) (match_dup 2)))
+ [(set (match_dup 4)
+ (match_dup 5))
(set (pc)
(if_then_else (match_op_dup 0
- [(reg:H8cc CC_REG) (const_int 0)])
+ [(match_dup 4) (const_int 0)])
(label_ref (match_dup 3)) (pc)))]
- "")
+ "
+{
+ machine_mode mode;
+
+ if (REG_P (operands[1])
+ && operands[2] == const0_rtx
+ && (GET_CODE (operands[0]) == EQ
+ || GET_CODE (operands[0]) == NE
+ || GET_CODE (operands[0]) == LT
+ || GET_CODE (operands[0]) == GE
+ /* Our tstxx insns will set ZN and clear V, so we can handle
+ a couple additional cases. */
+ || GET_CODE (operands[0]) == LE
+ || GET_CODE (operands[0]) == GT))
+ mode = E_CCZNmode;
+ else
+ mode = E_CCmode;
+ operands[4] = gen_rtx_REG (mode, CC_REG);
+ operands[5] = gen_rtx_COMPARE (mode, operands[1], operands[2]);
+}")
(define_insn "*branch_1"
[(set (pc)
@@ -506,6 +506,8 @@
{
if (GET_MODE (op) == mode
&& (GET_CODE (XEXP (op, 0)) != PRE_DEC
+ && GET_CODE (XEXP (op, 0)) != PRE_INC
+ && GET_CODE (XEXP (op, 0)) != POST_DEC
&& GET_CODE (XEXP (op, 0)) != POST_INC))
return 1;
return 0;
We seem to have lost much of the optimization of compare -> test insns at some point. While the H8 does not have a test style insn like the m68k, a nop move is an excellent substitute as it'll set the condition codes in an appropriate way. A nop move is 2 bytes for QI, HI and SI modes, while cmp<size> #0,rX is 2, 4 or 6 bytes for QI, HI and SI modes respectively. Obviously this can be a significant space savings. It'll help performance on real hardware as well, though I don't expect it to directly help simulator performance. This patch twiddles how we lower/split conditional branches so that we generate those nop moves instead of compares against zero when we're testing the Z and N bits. Note that these nop moves always clear the V bit, but leave C bit in whatever state it previously was, so effectively C is unknown. With ZN set and V always cleared, we can support things like LE 0 or GT 0 in addition to the more obvious EQ 0, NE 0, LT 0 and GE 0. In the process of testing this patch it became apparent that the "simple_memory_operand" predicate I added a while ago was allowing auto-inc modes that I wasn't aware the H8 supported (or I'd simply forgotten, it's been a while). So this patch fixes this minor goof as well. Committed to the trunk after the usual testing. Jeff commit 73c49ff53235d92aba4ee748fcb06b06e83e0b8f Author: Jeff Law <jeffreyalaw@gmail.com> Date: Tue Jul 6 10:55:53 2021 -0400 Use H8 nop moves as tst insns gcc * config/h8300/jumpcall.md (*branch): When possible, generate the comparison in CCZN mode. * config/h8300/predicates.md (simple_memory_operand): Reject all auto-increment addressing modes.