| Message ID | 7a70eca3-3442-2553-2434-08b5e00879a3@foss.arm.com |
|---|---|
| State | New |
| Headers | show |
Sorry, the bug cannot be reproduced on gcc-5-branch so it's probably better to only do a backport to gcc-6-branch. Ok for a backport to gcc-6-branch? Best regards, Thomas On 30/11/16 10:42, Thomas Preudhomme wrote: > Hi, > > Is this ok to backport to gcc-5-branch and gcc-6-branch? Patch applies cleanly > (patches attached for reference). > > > 2016-11-30 Thomas Preud'homme <thomas.preudhomme@arm.com> > > Backport from mainline > 2016-11-22 Thomas Preud'homme <thomas.preudhomme@arm.com> > > gcc/ > PR target/77904 > * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer > in save register mask if it is needed. > > gcc/testsuite/ > PR target/77904 > * gcc.target/arm/pr77904.c: New test. > > > Best regards, > > Thomas > > > On 22/11/16 10:45, Thomas Preudhomme wrote: >> On 17/11/16 09:11, Kyrill Tkachov wrote: >>> >>> On 17/11/16 08:56, Thomas Preudhomme wrote: >>>> On 16/11/16 10:30, Kyrill Tkachov wrote: >>>>> Hi Thomas, >>>>> >>>>> On 03/11/16 16:52, Thomas Preudhomme wrote: >>>>>> Hi, >>>>>> >>>>>> When using a callee-saved register to save the frame pointer the Thumb-1 >>>>>> prologue fails to save the callee-saved register before that. For ARM and >>>>>> Thumb-2 targets the frame pointer is handled as a special case but nothing is >>>>>> done for Thumb-1 targets. This patch adds the same logic for Thumb-1 targets. >>>>>> >>>>>> ChangeLog entries are as follow: >>>>>> >>>>>> *** gcc/ChangeLog *** >>>>>> >>>>>> 2016-11-02 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>>>> >>>>>> PR target/77904 >>>>>> * config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame pointer >>>>>> in save register mask if it is needed. >>>>>> >>>>> >>>>> s/mark/Mark/ >>>>> >>>>>> >>>>>> *** gcc/testsuite/ChangeLog *** >>>>>> >>>>>> 2016-11-02 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>>>> >>>>>> PR target/77904 >>>>>> * gcc.target/arm/pr77904.c: New test. >>>>>> >>>>>> >>>>>> Testing: Testsuite shows no regression when run with arm-none-eabi GCC >>>>>> cross-compiler for Cortex-M0 target. >>>>>> >>>>>> Is this ok for trunk? >>>>>> >>>>> >>>>> I'd ask for a bootstrap, but this code is Thumb-1 only so it wouldn't affect >>>>> anything. >>>> >>>> I can bootstrap for armv4t with --with-mode=thumb which would at least >>>> exercise the path. I'll try such a bootstrap on qemu. >>>> >>> >>> If you can get it to work, then yes please. >> >> Bootstrap came back clean so I've committed the patch (r242693). Thanks! >> >> Best regards, >> >> Thomas
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 83cb13d1195beb19d6301f5c83a7eb544a91d877..ae479a43fe8514f2eacb7d56f89916b48f720768 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -19390,6 +19390,10 @@ thumb1_compute_save_reg_mask (void) if (df_regs_ever_live_p (reg) && callee_saved_reg_p (reg)) mask |= 1 << reg; + /* Handle the frame pointer as a special case. */ + if (frame_pointer_needed) + mask |= 1 << HARD_FRAME_POINTER_REGNUM; + if (flag_pic && !TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM diff --git a/gcc/testsuite/gcc.target/arm/pr77904.c b/gcc/testsuite/gcc.target/arm/pr77904.c new file mode 100644 index 0000000000000000000000000000000000000000..76728c07e73350ce44160cabff3dd2fa7a6ef021 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr77904.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +__attribute__ ((noinline, noclone)) void +clobber_sp (void) +{ + __asm volatile ("" : : : "sp"); +} + +int +main (void) +{ + int ret; + + __asm volatile ("mov\tr4, #0xf4\n\t" + "mov\tr5, #0xf5\n\t" + "mov\tr6, #0xf6\n\t" + "mov\tr7, #0xf7\n\t" + "mov\tr0, #0xf8\n\t" + "mov\tr8, r0\n\t" + "mov\tr0, #0xfa\n\t" + "mov\tr10, r0" + : : : "r0", "r4", "r5", "r6", "r7", "r8", "r10"); + clobber_sp (); + + __asm volatile ("cmp\tr4, #0xf4\n\t" + "bne\tfail\n\t" + "cmp\tr5, #0xf5\n\t" + "bne\tfail\n\t" + "cmp\tr6, #0xf6\n\t" + "bne\tfail\n\t" + "cmp\tr7, #0xf7\n\t" + "bne\tfail\n\t" + "mov\tr0, r8\n\t" + "cmp\tr0, #0xf8\n\t" + "bne\tfail\n\t" + "mov\tr0, r10\n\t" + "cmp\tr0, #0xfa\n\t" + "bne\tfail\n\t" + "mov\t%0, #1\n" + "fail:\n\t" + "sub\tr0, #1" + : "=r" (ret) : :); + return ret; +}
Hi, Is this ok to backport to gcc-5-branch and gcc-6-branch? Patch applies cleanly (patches attached for reference). 2016-11-30 Thomas Preud'homme <thomas.preudhomme@arm.com> Backport from mainline 2016-11-22 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ PR target/77904 * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer in save register mask if it is needed. gcc/testsuite/ PR target/77904 * gcc.target/arm/pr77904.c: New test. Best regards, Thomas On 22/11/16 10:45, Thomas Preudhomme wrote: > On 17/11/16 09:11, Kyrill Tkachov wrote: >> >> On 17/11/16 08:56, Thomas Preudhomme wrote: >>> On 16/11/16 10:30, Kyrill Tkachov wrote: >>>> Hi Thomas, >>>> >>>> On 03/11/16 16:52, Thomas Preudhomme wrote: >>>>> Hi, >>>>> >>>>> When using a callee-saved register to save the frame pointer the Thumb-1 >>>>> prologue fails to save the callee-saved register before that. For ARM and >>>>> Thumb-2 targets the frame pointer is handled as a special case but nothing is >>>>> done for Thumb-1 targets. This patch adds the same logic for Thumb-1 targets. >>>>> >>>>> ChangeLog entries are as follow: >>>>> >>>>> *** gcc/ChangeLog *** >>>>> >>>>> 2016-11-02 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>>> >>>>> PR target/77904 >>>>> * config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame pointer >>>>> in save register mask if it is needed. >>>>> >>>> >>>> s/mark/Mark/ >>>> >>>>> >>>>> *** gcc/testsuite/ChangeLog *** >>>>> >>>>> 2016-11-02 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>>> >>>>> PR target/77904 >>>>> * gcc.target/arm/pr77904.c: New test. >>>>> >>>>> >>>>> Testing: Testsuite shows no regression when run with arm-none-eabi GCC >>>>> cross-compiler for Cortex-M0 target. >>>>> >>>>> Is this ok for trunk? >>>>> >>>> >>>> I'd ask for a bootstrap, but this code is Thumb-1 only so it wouldn't affect >>>> anything. >>> >>> I can bootstrap for armv4t with --with-mode=thumb which would at least >>> exercise the path. I'll try such a bootstrap on qemu. >>> >> >> If you can get it to work, then yes please. > > Bootstrap came back clean so I've committed the patch (r242693). Thanks! > > Best regards, > > Thomas