| Message ID | 77a010cf-b9c3-7f7f-06cc-393fbe8aff53@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Allow more loading of const vectors. | expand |
LGTM Robin Dapp via Gcc-patches <gcc-patches@gcc.gnu.org> 於 2023年5月19日 週五 19:07 寫道： > Hi, > > this fixes a rebase oversight regarding the loading > of vector constants. Added another test to properly > catch that in the future. > > Regards > Robin > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insns): Remove else. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: New test. > * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: New test. > --- > gcc/config/riscv/riscv.cc | 2 +- > .../gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 6 ++++++ > .../gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 6 ++++++ > 3 files changed, 13 insertions(+), 1 deletion(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 0d1b83f4315..0e874f0604d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -1295,7 +1295,7 @@ riscv_const_insns (rtx x) > The Wc0, Wc1 constraints are already covered by the > vi constraint so we do not need to check them here > separately. */ > - else if (TARGET_VECTOR && satisfies_constraint_vi (x)) > + if (TARGET_VECTOR && satisfies_constraint_vi (x)) > return 1; > > /* TODO: We may support more const vector in the future. */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c > new file mode 100644 > index 00000000000..631ea3bf268 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d > -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax > -fno-builtin" } */ > + > +#include "vmv-imm-template.h" > + > +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c > new file mode 100644 > index 00000000000..7ded6cc18d2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d > -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax > -fno-builtin" } */ > + > +#include "vmv-imm-template.h" > + > +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ > -- > 2.40.1 >
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0d1b83f4315..0e874f0604d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1295,7 +1295,7 @@ riscv_const_insns (rtx x) The Wc0, Wc1 constraints are already covered by the vi constraint so we do not need to check them here separately. */ - else if (TARGET_VECTOR && satisfies_constraint_vi (x)) + if (TARGET_VECTOR && satisfies_constraint_vi (x)) return 1; /* TODO: We may support more const vector in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c new file mode 100644 index 00000000000..631ea3bf268 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */ + +#include "vmv-imm-template.h" + +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c new file mode 100644 index 00000000000..7ded6cc18d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */ + +#include "vmv-imm-template.h" + +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */