From patchwork Tue Apr 7 14:13:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1267438 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48xTsm0CDmz9sSq for ; Wed, 8 Apr 2020 00:13:47 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9B6363877034; Tue, 7 Apr 2020 14:13:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 18663385C019 for ; Tue, 7 Apr 2020 14:13:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 18663385C019 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF00731B; Tue, 7 Apr 2020 07:13:42 -0700 (PDT) Received: from [10.57.25.163] (unknown [10.57.25.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 54E043F68F; Tue, 7 Apr 2020 07:13:42 -0700 (PDT) To: "gcc-patches@gcc.gnu.org" From: "Andre Vieira (lists)" Subject: [PATCH][GCC][Arm]: MVE: Fix vec extracts to memory Message-ID: <76d8dbd0-5507-cde1-9474-742bbcd6af43@arm.com> Date: Tue, 7 Apr 2020 15:13:41 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 Content-Language: en-US X-Spam-Status: No, score=-27.3 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch fixes vec extracts to memory that can arise from code as seen in the testcase added. The patch fixes this by allowing mem operands in the set of mve_vec_extract patterns, which given the only '=r' constraint will lead to the scalar value being written to a register and then stored in memory using scalar store pattern. Regression tested on arm-none-eabi. Is this OK for trunk? gcc/ChangeLog: 2020-04-07  Andre Vieira          * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set. gcc/testsuite/ChangeLog: 2020-04-07  Andre Vieira          * gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c: New test. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3c75f9ebc70d5765a59934b944955c757b6b2195..c49c14c4240838ce086f424f58726e2e94cf190e 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -10993,7 +10993,7 @@ (define_insn "mve_vld4q" ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f]) ;; (define_insn "mve_vec_extract" - [(set (match_operand: 0 "s_register_operand" "=r") + [(set (match_operand: 0 "nonimmediate_operand" "=r") (vec_select: (match_operand:MVE_VLD_ST 1 "s_register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] @@ -11011,7 +11011,7 @@ (define_insn "mve_vec_extract" [(set_attr "type" "mve_move")]) (define_insn "mve_vec_extractv2didi" - [(set (match_operand:DI 0 "s_register_operand" "=r") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r") (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] @@ -11024,7 +11024,7 @@ (define_insn "mve_vec_extractv2didi" if (elt == 0) return "vmov\t%Q0, %R0, %e1"; else - return "vmov\t%J0, %K0, %f1"; + return "vmov\t%Q0, %R0, %f1"; } [(set_attr "type" "mve_move")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c new file mode 100644 index 0000000000000000000000000000000000000000..12f2f2d38d3c2e189a9c06f21fc63e2c23e2e721 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c @@ -0,0 +1,40 @@ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3" } */ + +#include "arm_mve.h" + +uint8x16_t *vu8; +int8x16_t *vs8; +uint16x8_t *vu16; +int16x8_t *vs16; +uint32x4_t *vu32; +int32x4_t *vs32; +uint64x2_t *vu64; +int64x2_t *vs64; +float16x8_t *vf16; +float32x4_t *vf32; +uint8_t u8; +uint16_t u16; +uint32_t u32; +uint64_t u64; +int8_t s8; +int16_t s16; +int32_t s32; +int64_t s64; +float16_t f16; +float32_t f32; + +void foo (void) +{ + u8 = vgetq_lane (*vu8, 1); + u16 = vgetq_lane (*vu16, 1); + u32 = vgetq_lane (*vu32, 1); + u64 = vgetq_lane (*vu64, 1); + s8 = vgetq_lane (*vs8, 1); + s16 = vgetq_lane (*vs16, 1); + s32 = vgetq_lane (*vs32, 1); + s64 = vgetq_lane (*vs64, 1); + f16 = vgetq_lane (*vf16, 1); + f32 = vgetq_lane (*vf32, 1); +}