From patchwork Wed Dec 14 19:01:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anatoly Sokolov X-Patchwork-Id: 131457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 7CF7B1007D6 for ; Thu, 15 Dec 2011 06:01:25 +1100 (EST) Received: (qmail 26496 invoked by alias); 14 Dec 2011 19:01:22 -0000 Received: (qmail 26484 invoked by uid 22791); 14 Dec 2011 19:01:18 -0000 X-SWARE-Spam-Status: No, hits=-0.1 required=5.0 tests=AWL, BAYES_00, KAM_THEBAT, RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from contrabass.post.ru (HELO contrabass.corbina.net) (85.21.78.5) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 14 Dec 2011 19:01:03 +0000 Received: from corbina.ru (violin.corbina.net [195.14.50.30]) by contrabass.corbina.net (Postfix) with ESMTP id 1DF6EC9CD8; Wed, 14 Dec 2011 23:01:01 +0400 (MSK) Received: from [89.178.214.132] (account aesok@post.ru HELO Vista.beeline) by fe1-mc.corbina.ru (CommuniGate Pro SMTP 5.4.2) with ESMTPA id 56847790; Wed, 14 Dec 2011 23:01:01 +0400 Date: Wed, 14 Dec 2011 23:01:20 +0400 From: Anatoly Sokolov Message-ID: <753299673.20111214230120@post.ru> To: gcc-patches CC: nickc@redhat.com, rearnsha@arm.com Subject: [ARM] Hookize REGISTER_MOVE_COST and MEMORY_MOVE_COST MIME-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi. This patch removes obsolete REGISTER_MOVE_COST and MEMORY_MOVE_COST macros from the ARM back end in the GCC and introduces equivalent TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST target hooks. Bootstrapped and regression tested on arm-unknown-linux-gnueabi. OK to install? * config/arm/arm.h (REGISTER_MOVE_COST, MEMORY_MOVE_COST): Remove. * config/arm/arm.c (arm_memory_move_cost, arm_register_move_cost): New functions. (TARGET_REGISTER_MOVE_COST, TARGET_MEMORY_MOVE_COST): Define. Anatoly. Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 182109) +++ gcc/config/arm/arm.c (working copy) @@ -164,6 +164,8 @@ static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); static bool arm_rtx_costs (rtx, int, int, int, int *, bool); static int arm_address_cost (rtx, bool); +static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t); +static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool); static bool arm_memory_load_p (rtx); static bool arm_cirrus_insn_p (rtx); static void cirrus_reorg (rtx); @@ -363,6 +365,12 @@ #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST arm_adjust_cost +#undef TARGET_REGISTER_MOVE_COST +#define TARGET_REGISTER_MOVE_COST arm_register_move_cost + +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST arm_memory_move_cost + #undef TARGET_ENCODE_SECTION_INFO #ifdef ARM_PE #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info @@ -8484,6 +8492,63 @@ return true; } +/* Implement TARGET_REGISTER_MOVE_COST. + + Moves between FPA_REGS and GENERAL_REGS are two memory insns. + Moves between VFP_REGS and GENERAL_REGS are a single insn, but + it is typically more expensive than a single memory access. We set + the cost to less than two memory accesses so that floating + point to integer conversion does not go through memory. */ + +int +arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, + reg_class_t from, reg_class_t to) +{ + if (TARGET_32BIT) + { + if ((from == FPA_REGS && to != FPA_REGS) + || (from != FPA_REGS && to == FPA_REGS)) + return 20; + else if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to)) + || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to))) + return 15; + else if ((from == IWMMXT_REGS && to != IWMMXT_REGS) + || (from != IWMMXT_REGS && to == IWMMXT_REGS)) + return 4; + else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS) + return 20; + else if ((from == CIRRUS_REGS && to != CIRRUS_REGS) + || (from != CIRRUS_REGS && to == CIRRUS_REGS)) + return 20; + else + return 2; + } + else + { + if (from == HI_REGS || to == HI_REGS) + return 4; + else + return 2; + } +} + +/* Implement TARGET_MEMORY_MOVE_COST. */ + +int +arm_memory_move_cost (enum machine_mode mode, reg_class_t rclass, + bool in ATTRIBUTE_UNUSED) +{ + if (TARGET_32BIT) + return 10; + else + { + if (GET_MODE_SIZE (mode) < 4) + return 8; + else + return ((2 * GET_MODE_SIZE (mode)) * (rclass == LO_REGS ? 1 : 2)); + } +} + /* This function implements the target macro TARGET_SCHED_ADJUST_COST. It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK. It returns the new Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 182109) +++ gcc/config/arm/arm.h (working copy) @@ -1281,26 +1281,6 @@ /* If defined, gives a class of registers that cannot be used as the operand of a SUBREG that changes the mode of the object illegally. */ - -/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. - Moves between VFP_REGS and GENERAL_REGS are a single insn, but - it is typically more expensive than a single memory access. We set - the cost to less than two memory accesses so that floating - point to integer conversion does not go through memory. */ -#define REGISTER_MOVE_COST(MODE, FROM, TO) \ - (TARGET_32BIT ? \ - ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ - (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ - IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ - !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ - (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ - (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ - (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ - (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ - (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ - 2) \ - : \ - ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) /* Stack layout; function entry, exit and calling. */ @@ -1953,12 +1933,6 @@ ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ || (X) == arg_pointer_rtx) -/* Moves to and from memory are quite expensive */ -#define MEMORY_MOVE_COST(M, CLASS, IN) \ - (TARGET_32BIT ? 10 : \ - ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ - * (CLASS == LO_REGS ? 1 : 2))) - /* Try to generate sequences that don't involve branches, we can then use conditional instructions */ #define BRANCH_COST(speed_p, predictable_p) \