From patchwork Thu Jun 15 16:18:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 776359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wpTGC1cLmz9s5L for ; Fri, 16 Jun 2017 02:18:59 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="QzfTMlKA"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=HN4nXgpzG+lmJpYoO qzVl3VkkfM5JowFuJBPfRT7HAx+nfON2Dk2awBhuS3x5mZi/1iKOx+cJp61A8mLN RlVSD/p0v8cMwu2npc6a+bWM+/ZU3hlrUd9f+tDZoBhSmH3F2X7buUM+5Mb4Tldk B+yUySc9HyOsRkBoVwXO8JWphs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=dwpuLP+LTDzBiRkZfp1Lken 71eQ=; b=QzfTMlKAxKYsFdCEi1GR2X3mi/+8pf4tKw0yW6eJ3ASBnhKrad6mhIc cKraQE8KuDCIub2BA7GFDWmVkWQCvlAFfRrZc7d74YHm7d77Xd9lQKsmQAnCS7c8 N8m8aH0DhDEpkyN4vj4xjFKQgoVqtvIjo824TP6LM3so14bl8O7M= Received: (qmail 72333 invoked by alias); 15 Jun 2017 16:18:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 72323 invoked by uid 89); 15 Jun 2017 16:18:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Jun 2017 16:18:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BCE6344; Thu, 15 Jun 2017 09:18:46 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2EA013F41F; Thu, 15 Jun 2017 09:18:45 -0700 (PDT) Subject: Re: [PATCH, GCC/testsuite/ARM] Consistently check for neon in vect effective targets To: Christophe Lyon References: Cc: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme Message-ID: <7281afac-431b-cf38-95d6-8c1fbc8afdce@foss.arm.com> Date: Thu, 15 Jun 2017 17:18:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Hi, Conditions checked for ARM targets in vector-related effective targets are inconsistent: * sometimes arm*-*-* is checked * sometimes Neon is checked * sometimes arm_neon_ok and sometimes arm_neon is used for neon check * sometimes check_effective_target_* is used, sometimes is-effective-target This patch consolidate all of these check into using is-effective-target arm_neon and when little endian was checked, the check is kept. ChangeLog entry is as follows: *** gcc/testsuite/ChangeLog *** 2017-06-06 Thomas Preud'homme * lib/target-supports.exp (check_effective_target_vect_int): Replace current ARM check by ARM NEON's availability check. (check_effective_target_vect_intfloat_cvt): Likewise. (check_effective_target_vect_uintfloat_cvt): Likewise. (check_effective_target_vect_floatint_cvt): Likewise. (check_effective_target_vect_floatuint_cvt): Likewise. (check_effective_target_vect_shift): Likewise. (check_effective_target_whole_vector_shift): Likewise. (check_effective_target_vect_bswap): Likewise. (check_effective_target_vect_shift_char): Likewise. (check_effective_target_vect_long): Likewise. (check_effective_target_vect_float): Likewise. (check_effective_target_vect_perm): Likewise. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. (check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise. (check_effective_target_vect_widen_sum_qi_to_hi): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. (check_effective_target_vect_widen_mult_hi_to_si): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise. (check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise. (check_effective_target_vect_widen_shift): Likewise. (check_effective_target_vect_extract_even_odd): Likewise. (check_effective_target_vect_interleave): Likewise. (check_effective_target_vect_multiple_sizes): Likewise. (check_effective_target_vect64): Likewise. (check_effective_target_vect_max_reduc): Likewise. Testing: Testsuite shows no regression when targeting ARMv7-A with -mfpu=neon-fpv4 and -mfloat-abi=hard or when targeting Cortex-M3 with default FPU and float ABI (soft). Testing was done with both compare_tests and the updated dg-cmp-results proposed in https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01030.html Is this ok for trunk? Best regards, Thomas On 13/06/17 20:22, Christophe Lyon wrote: > Hi Thomas, > > On 13 June 2017 at 11:08, Thomas Preudhomme > wrote: >> Hi, >> >> Conditions checked for ARM targets in vector-related effective targets >> are inconsistent: >> >> * sometimes arm*-*-* is checked >> * sometimes Neon is checked >> * sometimes arm_neon_ok and sometimes arm_neon is used for neon check >> * sometimes check_effective_target_* is used, sometimes is-effective-target >> >> This patch consolidate all of these check into using is-effective-target >> arm_neon and when little endian was checked, the check is kept. >> >> ChangeLog entry is as follows: >> >> *** gcc/testsuite/ChangeLog *** >> >> 2017-06-06 Thomas Preud'homme >> >> * lib/target-supports.exp (check_effective_target_vect_int): Replace >> current ARM check by ARM NEON's availability check. >> (check_effective_target_vect_intfloat_cvt): Likewise. >> (check_effective_target_vect_uintfloat_cvt): Likewise. >> (check_effective_target_vect_floatint_cvt): Likewise. >> (check_effective_target_vect_floatuint_cvt): Likewise. >> (check_effective_target_vect_shift): Likewise. >> (check_effective_target_whole_vector_shift): Likewise. >> (check_effective_target_vect_bswap): Likewise. >> (check_effective_target_vect_shift_char): Likewise. >> (check_effective_target_vect_long): Likewise. >> (check_effective_target_vect_float): Likewise. >> (check_effective_target_vect_perm): Likewise. >> (check_effective_target_vect_perm_byte): Likewise. >> (check_effective_target_vect_perm_short): Likewise. >> (check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise. >> (check_effective_target_vect_widen_sum_qi_to_hi): Likewise. >> (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. >> (check_effective_target_vect_widen_mult_hi_to_si): Likewise. >> (check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise. >> (check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise. >> (check_effective_target_vect_widen_shift): Likewise. >> (check_effective_target_vect_extract_even_odd): Likewise. >> (check_effective_target_vect_interleave): Likewise. >> (check_effective_target_vect_multiple_sizes): Likewise. >> (check_effective_target_vect64): Likewise. >> (check_effective_target_vect_max_reduc): Likewise. >> >> Testing: Testsuite shows no regression when targeting ARMv7-A with >> -mfpu=neon-fpv4 and -mfloat-abi=hard or when targeting Cortex-M3 with >> default FPU and float ABI (soft). >> > > That's strange, my testing detects a syntax error: > > Executed from: gcc.dg/vect/vect.exp > gcc.dg/vect/slp-9.c: error executing dg-final: unbalanced close paren > > See http://people.linaro.org/~christophe.lyon/cross-validation/gcc-test-patches/249142-consistent_neon_check/report-build-info.html > for a full picture. > > Note that the cells with "BETTER" seem to be mostly several PASSes > becoming unsupported. > > Thanks, > > Christophe > >> Is this ok for trunk? >> >> Best regards, >> >> Thomas diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index ded6383cc1f9a1489cd83e1dace0c2fc48e252c3..aa8550c9d2cf0ae7e157d9c67fa06ad811651421 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2916,7 +2916,7 @@ proc check_effective_target_vect_int { } { || [istarget alpha*-*-*] || [istarget ia64-*-*] || [istarget aarch64*-*-*] - || [check_effective_target_arm32] + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && ([et-is-effective-target mips_loongson] || [et-is-effective-target mips_msa])) } { @@ -2944,8 +2944,7 @@ proc check_effective_target_vect_intfloat_cvt { } { if { [istarget i?86-*-*] || [istarget x86_64-*-*] || ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) } { set et_vect_intfloat_cvt_saved($et_index) 1 @@ -2987,8 +2986,7 @@ proc check_effective_target_vect_uintfloat_cvt { } { || ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) || [istarget aarch64*-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) } { set et_vect_uintfloat_cvt_saved($et_index) 1 @@ -3016,8 +3014,7 @@ proc check_effective_target_vect_floatint_cvt { } { if { [istarget i?86-*-*] || [istarget x86_64-*-*] || ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) } { set et_vect_floatint_cvt_saved($et_index) 1 @@ -3043,8 +3040,7 @@ proc check_effective_target_vect_floatuint_cvt { } { set et_vect_floatuint_cvt_saved($et_index) 0 if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) } { set et_vect_floatuint_cvt_saved($et_index) 1 @@ -4903,7 +4899,7 @@ proc check_effective_target_vect_shift { } { || [istarget ia64-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget aarch64*-*-*] - || [check_effective_target_arm32] + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && ([et-is-effective-target mips_msa] || [et-is-effective-target mips_loongson])) } { @@ -4921,7 +4917,7 @@ proc check_effective_target_whole_vector_shift { } { || [istarget ia64-*-*] || [istarget aarch64*-*-*] || [istarget powerpc64*-*-*] - || ([check_effective_target_arm32] + || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) || ([istarget mips*-*-*] && [et-is-effective-target mips_loongson]) } { @@ -4945,8 +4941,7 @@ proc check_effective_target_vect_bswap { } { } else { set et_vect_bswap_saved($et_index) 0 if { [istarget aarch64*-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon]) + || [is-effective-target arm_neon] } { set et_vect_bswap_saved($et_index) 1 } @@ -4969,7 +4964,7 @@ proc check_effective_target_vect_shift_char { } { set et_vect_shift_char_saved($et_index) 0 if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) - || [check_effective_target_arm32] + || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) } { set et_vect_shift_char_saved($et_index) 1 @@ -4987,10 +4982,10 @@ proc check_effective_target_vect_shift_char { } { proc check_effective_target_vect_long { } { if { [istarget i?86-*-*] || [istarget x86_64-*-*] - || (([istarget powerpc*-*-*] - && ![istarget powerpc-*-linux*paired*]) + || (([istarget powerpc*-*-*] + && ![istarget powerpc-*-linux*paired*]) && [check_effective_target_ilp32]) - || [check_effective_target_arm32] + || [is-effective-target arm_neon] || ([istarget sparc*-*-*] && [check_effective_target_ilp32]) || [istarget aarch64*-*-*] || ([istarget mips*-*-*] @@ -5025,7 +5020,7 @@ proc check_effective_target_vect_float { } { || [istarget aarch64*-*-*] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || [check_effective_target_arm32] } { + || [is-effective-target arm_neon] } { set et_vect_float_saved($et_index) 1 } } @@ -5174,7 +5169,7 @@ proc check_effective_target_vect_perm { } { verbose "check_effective_target_vect_perm: using cached result" 2 } else { set et_vect_perm_saved($et_index) 0 - if { [is-effective-target arm_neon_ok] + if { [is-effective-target arm_neon] || [istarget aarch64*-*-*] || [istarget powerpc*-*-*] || [istarget spu-*-*] @@ -5203,7 +5198,7 @@ proc check_effective_target_vect_perm_byte { } { verbose "check_effective_target_vect_perm_byte: using cached result" 2 } else { set et_vect_perm_byte_saved($et_index) 0 - if { ([is-effective-target arm_neon_ok] + if { ([is-effective-target arm_neon] && [is-effective-target arm_little_endian]) || ([istarget aarch64*-*-*] && [is-effective-target aarch64_little_endian]) @@ -5232,7 +5227,7 @@ proc check_effective_target_vect_perm_short { } { verbose "check_effective_target_vect_perm_short: using cached result" 2 } else { set et_vect_perm_short_saved($et_index) 0 - if { ([is-effective-target arm_neon_ok] + if { ([is-effective-target arm_neon] && [is-effective-target arm_little_endian]) || ([istarget aarch64*-*-*] && [is-effective-target aarch64_little_endian]) @@ -5264,8 +5259,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } { set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 0 if { [istarget powerpc*-*-*] || [istarget aarch64*-*-*] - || ([istarget arm*-*-*] && - [check_effective_target_arm_neon_ok]) + || [is-effective-target arm_neon] || [istarget ia64-*-*] } { set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 1 } @@ -5319,7 +5313,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { } else { set et_vect_widen_sum_qi_to_hi_saved($et_index) 0 if { [check_effective_target_vect_unpack] - || [check_effective_target_arm_neon_ok] + || [is-effective-target arm_neon] || [istarget ia64-*-*] } { set et_vect_widen_sum_qi_to_hi_saved($et_index) 1 } @@ -5377,7 +5371,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } { } if { [istarget powerpc*-*-*] || [istarget aarch64*-*-*] - || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } { + || [is-effective-target arm_neon] } { set et_vect_widen_mult_qi_to_hi_saved($et_index) 1 } } @@ -5414,8 +5408,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } { || [istarget ia64-*-*] || [istarget aarch64*-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok]) } { + || [is-effective-target arm_neon] } { set et_vect_widen_mult_hi_to_si_saved($et_index) 1 } } @@ -5439,8 +5432,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } { } else { set et_vect_widen_mult_qi_to_hi_pattern_saved($et_index) 0 if { [istarget powerpc*-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok] + || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) } { set et_vect_widen_mult_qi_to_hi_pattern_saved($et_index) 1 } @@ -5468,8 +5460,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } { || [istarget spu-*-*] || [istarget ia64-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok] + || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) } { set et_vect_widen_mult_hi_to_si_pattern_saved($et_index) 1 } @@ -5516,7 +5507,7 @@ proc check_effective_target_vect_widen_shift { } { verbose "check_effective_target_vect_widen_shift: using cached result" 2 } else { set et_vect_widen_shift_saved($et_index) 0 - if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } { + if { [is-effective-target arm_neon] } { set et_vect_widen_shift_saved($et_index) 1 } } @@ -6070,7 +6061,7 @@ proc check_effective_target_vect_extract_even_odd { } { set et_vect_extract_even_odd_saved($et_index) 0 if { [istarget aarch64*-*-*] || [istarget powerpc*-*-*] - || [is-effective-target arm_neon_ok] + || [is-effective-target arm_neon] || [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget ia64-*-*] || [istarget spu-*-*] @@ -6098,7 +6089,7 @@ proc check_effective_target_vect_interleave { } { set et_vect_interleave_saved($et_index) 0 if { [istarget aarch64*-*-*] || [istarget powerpc*-*-*] - || [is-effective-target arm_neon_ok] + || [is-effective-target arm_neon] || [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget ia64-*-*] || [istarget spu-*-*] @@ -6152,7 +6143,7 @@ proc check_effective_target_vect_multiple_sizes { } { set et_vect_multiple_sizes_saved($et_index) 0 if { [istarget aarch64*-*-*] - || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) + || [is-effective-target arm_neon] || (([istarget i?86-*-*] || [istarget x86_64-*-*]) && ([check_avx_available] && ![check_prefer_avx128])) } { set et_vect_multiple_sizes_saved($et_index) 1 @@ -6173,8 +6164,7 @@ proc check_effective_target_vect64 { } { verbose "check_effective_target_vect64: using cached result" 2 } else { set et_vect64_saved($et_index) 0 - if { ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok] + if { ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) || [istarget aarch64*-*-*] || [istarget sparc*-*-*] } { @@ -8187,7 +8177,7 @@ proc check_effective_target_builtin_eh_return { } { # Return 1 if the target supports max reduction for vectors. proc check_effective_target_vect_max_reduc { } { - if { [istarget aarch64*-*-*] || [istarget arm*-*-*] } { + if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] } { return 1 } return 0